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1. 发明授权

US07952453B2 Structure design for minimizing on-chip interconnect inductance 有权
标题翻译：用于最小化片上互连电感的结构设计
公开(公告)号：US07952453B2
公开(公告)日：2011-05-31
申请号：US12759836
申请日：2010-04-14
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01P3/08
CPC分类号： H01P3/08
摘要： A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.
摘要翻译：公开了一种包括信号线和接地线的半导体器件。信号线包括开口，并且接地线的至少一部分在信号线中的开口中。

2. 发明申请

US20080076258A1 METHOD FOR FABRICATING AIR GAP FOR SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的空气隙的方法
公开(公告)号：US20080076258A1
公开(公告)日：2008-03-27
申请号：US11533809
申请日：2006-09-21
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/7682 , H01L21/0206
摘要： A method for fabricating an interconnect structure in a semiconductor device. A masking layer is formed on a dielectric layer formed on a substrate, having at least one opening. The opening is transferred into the dielectric layer. A Plasma stripping process is performed to remove the masking layer, such that a damaged sidewall portion of the dielectric layer surrounding the opening therein is formed. The opening in the dielectric layer is filled with a conductive element. The damaged sidewall portion of the dielectric layer is removed to form a gap between the dielectric layer and the conductive element, wherein substances from removal of the damaged sidewall portion of the dielectric layer are formed on the conductive element. The substances are removed using a citric acid solution.
摘要翻译：一种在半导体器件中制造互连结构的方法。在形成在基板上的电介质层上形成有至少一个开口的掩模层。开口转移到电介质层中。进行等离子体剥离处理以去除掩模层，从而形成围绕其中的开口的电介质层的受损侧壁部分。电介质层中的开口填充有导电元件。去除电介质层损坏的侧壁部分，以形成电介质层和导电元件之间的间隙，其中去除导电元件上介质层损坏的侧壁部分的物质。使用柠檬酸溶液除去物质。

3. 发明申请

US20070166887A1 Semiconductor device structure and methods of manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20070166887A1
公开(公告)日：2007-07-19
申请号：US11333618
申请日：2006-01-17
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng , Shin-Puu Jeng
IPC分类号： H01L21/82
CPC分类号： H01L27/0203 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.
摘要翻译：提供了一种生成半导体器件阵列布局的方法。提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

4. 发明授权

US07651893B2 Metal electrical fuse structure 有权
标题翻译：金属电熔丝结构
公开(公告)号：US07651893B2
公开(公告)日：2010-01-26
申请号：US11320233
申请日：2005-12-27
申请人： Hsueh-Chung Chen , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Shang-Yun Hou
发明人： Hsueh-Chung Chen , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Shang-Yun Hou
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An electrical fuse and a method for forming the same are provided. The electrical fuse includes a dielectric layer over a shallow trench isolation region and a contact plug extending from a top surface of the dielectric layer to the shallow trench isolation region, wherein the contact plug comprises a middle portion substantially narrower than the two end portions. The contact plug forms a fuse element. The electrical fuse further includes two metal lines in a metallization layer on the dielectric layer, wherein each of the two metal lines is connected to different ones of the end portions of the contact plug.
摘要翻译：提供电熔丝及其形成方法。电熔丝包括在浅沟槽隔离区域上的电介质层和从电介质层的顶表面延伸到浅沟槽隔离区域的接触插塞，其中接触插塞包括基本上比两个端部部分窄的中间部分。接触插头形成熔丝元件。电熔丝还包括在电介质层上的金属化层中的两条金属线，其中两条金属线中的每一条连接到接触插塞的不同端部。

5. 发明申请

US20070145515A1 Metal electrical fuse structure 有权
标题翻译：金属电熔丝结构
公开(公告)号：US20070145515A1
公开(公告)日：2007-06-28
申请号：US11320233
申请日：2005-12-27
申请人： Hsueh-Chung Chen , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Shang-Yun Hou
发明人： Hsueh-Chung Chen , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Shang-Yun Hou
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An electrical fuse and a method for forming the same are provided. The electrical fuse includes a dielectric layer over a shallow trench isolation region and a contact plug extending from a top surface of the dielectric layer to the shallow trench isolation region, wherein the contact plug comprises a middle portion substantially narrower than the two end portions. The contact plug forms a fuse element. The electrical fuse further includes two metal lines in a metallization layer on the dielectric layer, wherein each of the two metal lines is connected to different ones of the end portions of the contact plug.
摘要翻译：提供电熔丝及其形成方法。电熔丝包括在浅沟槽隔离区域上的电介质层和从电介质层的顶表面延伸到浅沟槽隔离区域的接触插塞，其中接触插塞包括基本上比两个端部部分窄的中间部分。接触插头形成熔丝元件。电熔丝还包括在电介质层上的金属化层中的两条金属线，其中两条金属线中的每一条连接到接触插塞的不同端部。

6. 发明申请

US20100194501A1 STRUCTURE DESIGN FOR MINIMIZING ON-CHIP INTERCONNECT INDUCTANCE 有权
标题翻译：用于最小化片上互连电感的结构设计
公开(公告)号：US20100194501A1
公开(公告)日：2010-08-05
申请号：US12759836
申请日：2010-04-14
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01P3/08
CPC分类号： H01P3/08
摘要： A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.
摘要翻译：公开了一种包括信号线和接地线的半导体器件。信号线包括开口，并且接地线的至少一部分在信号线中的开口中。

7. 发明授权

US07714443B2 Pad structure design with reduced density 有权
标题翻译：垫结构设计，密度降低
公开(公告)号：US07714443B2
公开(公告)日：2010-05-11
申请号：US11458501
申请日：2006-07-19
申请人： Hsien-Wei Chen , Anbiarshy Wu , Shih-Hsun Hsu , Shang-Yun Hou , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Anbiarshy Wu , Shih-Hsun Hsu , Shang-Yun Hou , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01L23/52
CPC分类号： H01L21/76895 , H01L22/34 , H01L23/5226 , H01L24/03 , H01L24/05 , H01L2224/05093 , H01L2224/05096 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01074 , H01L2924/14 , H01L2924/30105
摘要： An interconnect structure includes at least a first interconnect layer and a second interconnect layer. Each of the first and second interconnect layers has a pad structure and each pad structure has a respective pad density. The pad density of the pad structure of the second interconnect layer is different from the pad density of the pad structure of the first interconnect layer. The pad structures of the first and second interconnect layers are connected to each other.
摘要翻译：互连结构至少包括第一互连层和第二互连层。第一和第二互连层中的每一个具有焊盘结构，并且每个焊盘结构具有相应的焊盘密度。第二互连层的焊盘结构的焊盘密度不同于第一互连层的焊盘结构的焊盘密度。第一和第二互连层的焊盘结构彼此连接。

8. 发明授权

US07705696B2 Structure design for minimizing on-chip interconnect inductance 有权
标题翻译：用于最小化片上互连电感的结构设计
公开(公告)号：US07705696B2
公开(公告)日：2010-04-27
申请号：US11688903
申请日：2007-03-21
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01P3/08
CPC分类号： H01P3/08
摘要： A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.
摘要翻译：公开了一种包括信号线和接地线的半导体器件。信号线包括开口，并且接地线的至少一部分在信号线中的开口中。

9. 发明授权

US07512924B2 Semiconductor device structure and methods of manufacturing the same 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US07512924B2
公开(公告)日：2009-03-31
申请号：US11333618
申请日：2006-01-17
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng , Shin-Puu Jeng
IPC分类号： G06F17/50
CPC分类号： H01L27/0203 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.
摘要翻译：提供了一种生成半导体器件阵列布局的方法。提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

10. 发明申请

US20070015365A1 Method and apparatus for enhanced CMP planarization using surrounded dummy design 有权
公开(公告)号：US20070015365A1
公开(公告)日：2007-01-18
申请号：US11181433
申请日：2005-07-14
申请人： Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
发明人： Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
IPC分类号： H01L21/461
CPC分类号： H01L21/3212 , H01L21/31053
摘要： In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

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