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1. 发明授权

US07919384B2 Method of making planar-type bottom electrode for semiconductor device 有权
标题翻译：制造半导体器件的平面型底电极的方法
公开(公告)号：US07919384B2
公开(公告)日：2011-04-05
申请号：US12050649
申请日：2008-03-18
申请人： Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
发明人： Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
IPC分类号： H01L21/20
CPC分类号： H01L28/91
摘要： A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.
摘要翻译：公开了制造半导体器件的平面型底电极的方法。在基板上形成牺牲层结构。在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。绝缘层分别分开彼此分离的底部电极层。最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。

2. 发明授权

US06393210B1 Rapid thermal processing method and apparatus 有权
标题翻译：快速热处理方法和装置
公开(公告)号：US06393210B1
公开(公告)日：2002-05-21
申请号：US09469146
申请日：1999-12-21
申请人： Hsiao-Che Wu
发明人： Hsiao-Che Wu
IPC分类号： F26B1900
CPC分类号： H01L21/67115
摘要： An apparatus for the rapid thermal processing of a semiconductor wafer is disclosed. The apparatus includes a preheat unit for preheating a gas composition, and a RTP reactor having a processing chamber and a heat source for heating the wafer. The processing chamber has a wafer holder, and a gas inlet and a gas outlet through which the preheated gas composition flows in and out of the processing chamber.
摘要翻译：公开了一种用于半导体晶片快速热处理的装置。该装置包括用于预热气体组合物的预热单元，以及具有用于加热晶片的处理室和热源的RTP反应器。处理室具有晶片保持器，以及气体入口和气体出口，预热气体组合物通过该出口和气体出口流入和流出处理室。

3. 发明申请

US20080076241A1 Method for reducing stress between a conductive layer and a mask layer and use of the same 审中-公开
标题翻译：用于降低导电层和掩模层之间的应力的方法及其用途
公开(公告)号：US20080076241A1
公开(公告)日：2008-03-27
申请号：US11641131
申请日：2006-12-19
申请人： Tsung-Hsun Yang , Hsiao-Che Wu , Feng-Chun Chen , Chien-Hsun Pan
发明人： Tsung-Hsun Yang , Hsiao-Che Wu , Feng-Chun Chen , Chien-Hsun Pan
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/3211
摘要： A method for reducing stress between a conductive layer and a mask layer is provided. The method for reducing stress comprises a step of performing a plasma treatment with a nitrogen-containing gas to modify a surface of the conductive layer prior to the formation of the mask layer upon the surface. The method is useful for the manufacture of a gate, and the method for manufacturing the gate comprises the steps of providing a substrate; and sequentially depositing an oxide layer, a conductive layer, and a mask layer on the substrate to form a gate stack structure. The conductive layer is subjected to a surface plasma treatment with a nitrogen-containing gas prior to depositing the mask layer to modify its surface.
摘要翻译：提供了一种用于减小导电层和掩模层之间的应力的方法。减少应力的方法包括在表面形成掩模层之前，用含氮气体进行等离子体处理以改变导电层的表面的步骤。该方法对于制造栅极是有用的，并且用于制造栅极的方法包括以下步骤：提供基板; 并在衬底上依次沉积氧化物层，导电层和掩模层以形成栅叠层结构。在沉积掩模层以改变其表面之前，用含氮气体对导电层进行表面等离子体处理。

4. 发明申请

US20070210374A1 VERTICAL-TYPE SURROUNDING GATE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：垂直型环形半导体器件
公开(公告)号：US20070210374A1
公开(公告)日：2007-09-13
申请号：US11308906
申请日：2006-05-25
申请人： Hsiao-Che Wu
发明人： Hsiao-Che Wu
IPC分类号： H01L31/00
CPC分类号： H01L29/7827 , H01L29/456 , H01L29/517 , H01L29/518 , H01L29/66666
摘要： A vertical-type surrounding gate semiconductor device is described. The semiconductor device comprises a pillar substrate, a collar oxide layer, a metal layer, a drain region, a ground line, a source region, a bit line, a word line, a gate and a gate dielectric layer. The ground line is formed in an opening of the pillar substrate and electrically connected to the pillar substrate, and covers the collar oxide layer and the metal layer. The drain region is formed on the top of the pillar substrate and in the upper portion of the opening. The gate is formed among the word line, the bit line and the pillar substrate. The gate dielectric layer is formed among the gate, the source region, the drain region, the bit line and the pillar substrate.
摘要翻译：描述了垂直型周围栅极半导体器件。该半导体器件包括柱状基底，环状氧化物层，金属层，漏极区域，接地线，源极区域，位线，字线，栅极和栅极电介质层。接地线形成在支柱基板的开口部，与柱基板电连接，覆盖环状氧化物层和金属层。漏极区域形成在支柱基板的顶部和开口的上部。栅极形成在字线，位线和柱基板之间。在栅极，源极区域，漏极区域，位线和柱状基板之间形成栅极电介质层。

5. 发明申请

US20060035428A1 DYNAMIC RANDOM ACCESS MEMORY CELL AND FABRICATING METHOD THEREOF 失效
公开(公告)号：US20060035428A1
公开(公告)日：2006-02-16
申请号：US10711574
申请日：2004-09-25
申请人： Hsiao-Che Wu
发明人： Hsiao-Che Wu
IPC分类号： H01L21/8244
CPC分类号： H01L27/10867 , H01L27/10838 , H01L27/1087 , H01L27/10876 , H01L29/66181 , H01L29/945
摘要： A method of fabricating a dynamic random access memory cell is provided. A substrate having a patterned mask layer thereon and a deep trench therein is provided. The patterned mask layer exposes the deep trench. A deep trench capacitor is formed inside the deep trench. Thereafter, a trench is formed in the substrate on one side of the deep trench capacitor. The trench exposes a portion of the upper electrode of the deep trench capacitor and a portion of the substrate. After that, a semiconductor strip is formed in the trench. A gate dielectric layer is formed over the substrate to cover the exposed semiconductor strip and the substrate. A gate is formed over the gate dielectric layer such that the gate and the semiconductor strip crosses over each other, and the gate-covered portion of the semiconductor strip serves as a channel region.

6. 发明申请

US20090023264A1 METHOD OF MAKING PLANAR-TYPE BOTTOM ELECTRODE FOR SEMICONDUCTOR DEVICE 有权
标题翻译：制造用于半导体器件的平面型底电极的方法
公开(公告)号：US20090023264A1
公开(公告)日：2009-01-22
申请号：US12050649
申请日：2008-03-18
申请人： Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
发明人： Hsiao-Che Wu , Ming-Yen Li , Wen-Li Tsai
IPC分类号： H01L21/02
CPC分类号： H01L28/91
摘要： A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.
摘要翻译：公开了制造半导体器件的平面型底电极的方法。在基板上形成牺牲层结构。在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。绝缘层分别分开彼此分离的底部电极层。最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。

7. 发明申请

US20080199614A1 Method for improving atomic layer deposition performance and apparatus thereof 审中-公开
标题翻译：提高原子层沉积性能的方法及其装置
公开(公告)号：US20080199614A1
公开(公告)日：2008-08-21
申请号：US11790432
申请日：2007-04-25
申请人： Ming-Yen Li , Hsiao-Che Wu
发明人： Ming-Yen Li , Hsiao-Che Wu
IPC分类号： C23C16/00
CPC分类号： C23C16/45544 , C23C16/4557 , C23C16/45572 , C23C16/46 , C23C16/463
摘要： A method for improving atomic layer deposition (ALD) performance and an apparatus thereof are disclosed. The apparatus alternates the process temperature of the different ALD steps rapidly, and the process temperature of each step is determined in accordance with the specific precursor and the substrate surface used. In case a higher process temperature is needed, a plurality of heating units of the apparatus increases and keeps the temperature of the deposited substrate to complete surface reaction. When the lower process temperature is needful for the next ALD step, the heating units are turned off to reduce the temperature of the deposited substrate and a gas flow puffed to the heater and the deposited substrate to assist in temperature cooling.
摘要翻译：公开了一种改善原子层沉积（ALD）性能的方法及其装置。该装置可以快速地改变不同ALD步骤的工艺温度，并根据具体的前体和所使用的基材表面确定每个步骤的工艺温度。在需要更高的工艺温度的情况下，该装置的多个加热单元增加并保持沉积的基板的温度以完成表面反应。当下一个ALD步骤需要较低的工艺温度时，加热单元被关闭以降低沉积的基板的温度，并将气流膨胀到加热器和沉积的基板以辅助温度冷却。

8. 发明申请

US20080111212A1 Capacitance structure of a semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件的电容结构及其制造方法
公开(公告)号：US20080111212A1
公开(公告)日：2008-05-15
申请号：US11598391
申请日：2006-11-13
申请人： Hsiao-Che Wu
发明人： Hsiao-Che Wu
IPC分类号： H01L27/00 , H01L21/77
CPC分类号： H01L28/91 , H01L27/0805 , H01L27/10852
摘要： A capacitance structure of a semiconductor device and a method for manufacturing the structure are provided. The capacitance structure comprises a plurality of capacitance elements and a plurality of supports. Each of the capacitance elements has a column, and each of the supports is disposed between two adjacent columns by partially connecting onto the outer surface of each of the two adjacent columns. Thereby, the mechanical properties of the capacitance structure can be enhanced.
摘要翻译：提供半导体器件的电容结构和制造该结构的方法。电容结构包括多个电容元件和多个支撑件。每个电容元件具有一列，并且每个支撑件通过部分地连接到两个相邻列中的每一个的外表面上而设置在两个相邻的列之间。由此，可以提高电容结构的机械特性。

9. 发明申请

US20080102207A1 Gas delivering system for in situ thermal treatment and thin film deposition and use of the same 审中-公开
标题翻译：用于原位热处理和薄膜沉积的气体输送系统及其使用
公开(公告)号：US20080102207A1
公开(公告)日：2008-05-01
申请号：US11715619
申请日：2007-03-08
申请人： Yu-Min Tsai , Hsiao-Che Wu , Wen-Li Tsai
发明人： Yu-Min Tsai , Hsiao-Che Wu , Wen-Li Tsai
IPC分类号： C23C16/00 , F16K21/00
CPC分类号： C23C16/45565 , C23C16/45572 , C23C16/481 , H01L21/67109 , H01L21/67115 , Y10T137/9464
摘要： A gas delivering system for an in situ thermal treatment, a thin film deposition and a use of the same are provided. The gas delivering system integrates a thermal treatment system therein so that a thin film deposition and a by rapid thermal annealing can be performed alternatively on a wafer in a reaction chamber. Accordingly, the density of the thin film can be improved and the thermal budget of the process can be reduced.
摘要翻译：提供了一种用于原位热处理，薄膜沉积及其使用的气体输送系统。气体输送系统将其中的热处理系统集成在一起，可以在反应室中的晶片上交替地进行薄膜沉积和快速热退火。因此，可以提高薄膜的密度，并且可以降低该方法的热预算。

10. 发明授权

US07312131B2 Method for forming multilayer electrode capacitor 失效
标题翻译：多层电极电容器形成方法
公开(公告)号：US07312131B2
公开(公告)日：2007-12-25
申请号：US10998929
申请日：2004-11-30
申请人： Hsiao-Che Wu
发明人： Hsiao-Che Wu
IPC分类号： H01L21/20
CPC分类号： H01L29/66181 , H01L21/76895 , H01L27/10855 , H01L27/10867 , H01L28/91 , H01L29/417 , H01L29/945
摘要： A method of forming a multilayer electrode capacitor is described. A trench is formed in a substrate or in an insulator layer. Two sets of conductive layers are deposited on the inner surface of the trench. The first set of conductive layers is electrically connected to each other, and so is the second set of conductive layers. Each of the second set of conductive layers is inserted between two first conductive layers, and dielectric layers are interposed between two conductive layers to form a multilayer electrode capacitor.
摘要翻译：描述形成多层电极电容器的方法。在衬底或绝缘体层中形成沟槽。两组导电层沉积在沟槽的内表面上。第一组导电层彼此电连接，第二组导电层也相互电连接。第二组导电层中的每一个插入在两个第一导电层之间，并且介电层插入在两个导电层之间以形成多层电极电容器。

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