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1. 发明授权

US08995100B2 Configurable electrostatic discharging power clamp and related integrated circuit 有权
标题翻译：可配置静电放电电源钳及相关集成电路
公开(公告)号：US08995100B2
公开(公告)日：2015-03-31
申请号：US13430649
申请日：2012-03-26
申请人： Hsiang-Ming Chou , Kuo-Liang Pan , Chien-Feng Tseng , Yi-Chiu Tsai , Chien-Shao Tang , Hsin-Han Chen
发明人： Hsiang-Ming Chou , Kuo-Liang Pan , Chien-Feng Tseng , Yi-Chiu Tsai , Chien-Shao Tang , Hsin-Han Chen
IPC分类号： H02H3/22 , H02H9/04 , H01L27/02
CPC分类号： H02H9/046 , H01L27/0251 , H01L27/0266
摘要： There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.
摘要翻译：提供了一种集成电路，其包括根据本发明的实施例的输出驱动器和可配置静电放电（ESD）功率钳位元件。输出驱动器包括具有第一导电类型并电连接到第一电力轨的第一半导体元件; 以及具有不同于第一导电类型的第二导电类型并电连接到第二电力轨的第二半导体元件。具体地，可配置的ESD功率钳位元件耦合在第一电力轨道和第二电力轨道之间以在被配置为第一硬件状态时提供ESD保护，并且当配置在第二硬件状态时形成输出驱动器的一部分，从而增加集成电路的设计灵活性。

2. 发明申请

US20130249046A1 CONFIGURABLE ELECTROSTATIC DISCHARGING POWER CLAMP AND RELATED INTEGRATED CIRCUIT 有权
标题翻译：可配置静电放电电源钳和相关集成电路
公开(公告)号：US20130249046A1
公开(公告)日：2013-09-26
申请号：US13430649
申请日：2012-03-26
申请人： Hsiang-Ming Chou , Kuo-Liang Pan , Chien-Feng Tseng , Yi-Chiu Tsai , Chien-Shao Tang , Hsin-Han Chen
发明人： Hsiang-Ming Chou , Kuo-Liang Pan , Chien-Feng Tseng , Yi-Chiu Tsai , Chien-Shao Tang , Hsin-Han Chen
IPC分类号： H01L29/06 , H01L21/768
CPC分类号： H02H9/046 , H01L27/0251 , H01L27/0266
摘要： There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.
摘要翻译：提供了一种集成电路，其包括根据本发明的实施例的输出驱动器和可配置静电放电（ESD）功率钳位元件。输出驱动器包括具有第一导电类型并电连接到第一电力轨的第一半导体元件; 以及具有不同于第一导电类型的第二导电类型并电连接到第二电力轨的第二半导体元件。具体地，可配置的ESD功率钳位元件耦合在第一电力轨道和第二电力轨道之间以在被配置为第一硬件状态时提供ESD保护，并且当配置在第二硬件状态时形成输出驱动器的一部分，从而增加集成电路的设计灵活性。

3. 发明授权

US5578516A High capacitance dynamic random access memory manufacturing process 失效
标题翻译：高电容动态随机存取存储器制造工艺
公开(公告)号：US5578516A
公开(公告)日：1996-11-26
申请号：US499745
申请日：1995-07-07
申请人： Hsiang-Ming Chou
发明人： Hsiang-Ming Chou
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method for manufacturing an array of dynamic random access memory (DRAM) cells having high capacitance stacked capacitors, is accomplished. The method involves forming node contact openings to the capacitor source/drain contact areas of the field effect transistors, and forming the capacitor bottom electrodes using patterned layers of heavily doped and undoped polysilicon. The selective etch property of the heavily doped polysilicon to the undoped polysilicon is used to form bottom electrodes having sidewall spacers extending upward and increasing the effective capacitor area. After doping the bottom electrode by either ion implantation or out-diffusion, the stacked capacitors on the array of DRAM cells is completed by forming an inter-electrode dielectric layer on the bottom electrode surfaces and forming a top electrodes from a patterned doped polysilicon layer.
摘要翻译：实现了具有高电容堆叠电容器的动态随机存取存储器（DRAM）单元阵列的制造方法。该方法包括在场效应晶体管的电容器源极/漏极接触区域形成节点接触开口，以及使用重掺杂和未掺杂多晶硅的图案化层形成电容器底部电极。重掺杂多晶硅对未掺杂多晶硅的选择性蚀刻性质用于形成具有向上延伸的侧壁间隔并增加有效电容器面积的底部电极。在通过离子注入或外扩散掺杂底部电极之后，通过在底部电极表面上形成电极间介电层并从图案化的掺杂多晶硅层形成顶部电极来完成DRAM单元阵列上的层叠电容器。

4. 发明授权

US5231052A Process for forming a multilayer polysilicon semiconductor electrode 失效
标题翻译：用于形成多层多晶硅半导体电极的工艺
公开(公告)号：US5231052A
公开(公告)日：1993-07-27
申请号：US655123
申请日：1991-02-14
申请人： Chih-Yuan Lu , Hsiang-Ming Chou
发明人： Chih-Yuan Lu , Hsiang-Ming Chou
IPC分类号： H01L21/768 , H01L23/485
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76847 , H01L21/76877 , H01L23/485 , H01L2924/0002 , Y10S438/97
摘要： A method for forming a multilayer contact to a device region through an insulating layered structure is described. An opening is formed through the insulating layered structure to the device region. A barrier metal layer is deposited over the device region and the insulating layered structure both above and on the sides of the opening. An in situ doped polysilicon layer is deposited over the barrier metal layer. A thin layer of metal is deposited over the polysilicon layer. The remaining portion of the opening is filled and the thin layer of metal is covered with undoped polysilicon. The undoped polysilicon is etched until the thin metal film is reached to thereby leave the opening filled. An aluminium metallurgical layer is deposited thereover to complete the multilayer contact.
摘要翻译：描述了通过绝缘分层结构形成到器件区域的多层接触的方法。通过绝缘层状结构向器件区域形成开口。阻挡金属层沉积在开口的上方和侧面上的器件区域和绝缘层状结构上。在阻挡金属层上沉积原位掺杂的多晶硅层。在多晶硅层上沉积薄层的金属。填充开口的剩余部分，金属的薄层被未掺杂的多晶硅覆盖。蚀刻未掺杂的多晶硅直到达到薄金属膜，从而使开口填充。在其上沉积铝冶金层以完成多层接触。

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