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1. 发明申请

US20100295009A1 Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane 有权
标题翻译：具有垂直通道访问晶体管和存储器平面的相变存储单元
公开(公告)号：US20100295009A1
公开(公告)日：2010-11-25
申请号：US12471287
申请日：2009-05-22
申请人： Hsiang-Lan Lung , Chung H. Lam , Ming-Hsiu Lee , Bipin Rajendran
发明人： Hsiang-Lan Lung , Chung H. Lam , Ming-Hsiu Lee , Bipin Rajendran
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的对应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻多行字线中的字线。相应的字线用作场效应晶体管的栅极。电介质将对应的字线与沟道区分开。存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

2. 发明申请

US20100181649A1 POLYSILICON PILLAR BIPOLAR TRANSISTOR WITH SELF-ALIGNED MEMORY ELEMENT 有权
标题翻译：具有自对准记忆元件的多晶硅柱状双极晶体管
公开(公告)号：US20100181649A1
公开(公告)日：2010-07-22
申请号：US12357912
申请日：2009-01-22
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1625 , H01L45/1683
摘要： Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.
摘要翻译：本文描述了具有与双极结晶体管存取装置的发射极自对准的存储元件的存储单元以及用于制造这种装置的方法。如本文所述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括双极结型晶体管，其包括由掺杂多晶硅柱构成的发射极。存储单元包括在发射器上的绝缘元件，并且具有延伸穿过绝缘层的开口，开口以发射器为中心。存储单元还包括在开口内的存储元件并电耦合到发射器。

3. 发明申请

US20100176362A1 POLYSILICON PLUG BIPOLAR TRANSISTOR FOR PHASE CHANGE MEMORY 有权
标题翻译：用于相变存储器的多晶硅插头双极晶体管
公开(公告)号：US20100176362A1
公开(公告)日：2010-07-15
申请号：US12353219
申请日：2009-01-13
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung H. Lam
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung H. Lam
IPC分类号： H01L29/73 , H01L47/00 , H01L21/8222 , H01L21/8229
CPC分类号： H01L45/04 , G11C13/0004 , H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.
摘要翻译：本文描述了存储器件和制造方法。本文描述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极接触多个字线中的对应字线以限定pn结。双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

4. 发明授权

US08237144B2 Polysilicon plug bipolar transistor for phase change memory 有权
标题翻译：用于相变存储器的多晶硅插头双极晶体管
公开(公告)号：US08237144B2
公开(公告)日：2012-08-07
申请号：US13252152
申请日：2011-10-03
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung H. Lam
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung H. Lam
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , G11C13/0004 , H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.
摘要翻译：本文描述了存储器件和制造方法。本文描述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极接触多个字线中的对应字线以限定pn结。双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

5. 发明申请

US20120018845A1 Polysilicon Plug Bipolar Transistor For Phase Change Memory 有权
标题翻译：用于相变存储器的多晶硅插头双极晶体管
公开(公告)号：US20120018845A1
公开(公告)日：2012-01-26
申请号：US13252152
申请日：2011-10-03
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung H. Lam
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung H. Lam
IPC分类号： H01L29/73
CPC分类号： H01L45/04 , G11C13/0004 , H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.
摘要翻译：本文描述了存储器件和制造方法。本文描述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极接触多个字线中的对应字线以限定pn结。双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

6. 发明授权

US08933536B2 Polysilicon pillar bipolar transistor with self-aligned memory element 有权
标题翻译：具有自对准存储元件的多晶硅柱双极晶体管
公开(公告)号：US08933536B2
公开(公告)日：2015-01-13
申请号：US12357912
申请日：2009-01-22
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
IPC分类号： H01L27/082 , H01L27/102 , H01L27/24 , H01L45/00
CPC分类号： H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1625 , H01L45/1683
摘要： Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.
摘要翻译：本文描述了具有与双极结晶体管存取装置的发射极自对准的存储元件的存储单元以及用于制造这种装置的方法。如本文所述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括双极结型晶体管，其包括由掺杂多晶硅柱构成的发射极。存储单元包括在发射器上的绝缘元件，并且具有延伸穿过绝缘层的开口，开口以发射器为中心。存储单元还包括在开口内的存储元件并电耦合到发射器。

7. 发明申请

US20090268507A1 PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURE 失效
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090268507A1
公开(公告)日：2009-10-29
申请号：US12111258
申请日：2008-04-29
申请人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： G11C11/00 , H01S4/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/1253 , Y10T29/49002
摘要： A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode.
摘要翻译：公开了一种相变存储器控制环下电极。下电极包括与相变存储元件热接触的外环电极，设置在外环电极内并与相变存储元件接触的内种子层，以及耦合到外环电极的导电底层。

8. 发明授权

US07868313B2 Phase change memory device and method of manufacture 失效
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07868313B2
公开(公告)日：2011-01-11
申请号：US12111258
申请日：2008-04-29
申请人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/1253 , Y10T29/49002
摘要： A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode.
摘要翻译：公开了一种相变存储器控制环下电极。下电极包括与相变存储元件热接触的外环电极，设置在外环电极内并与相变存储元件接触的内种子层，以及耦合到外环电极的导电底层。

9. 发明授权

US07944740B2 Multi-level cell programming of PCM by varying the reset amplitude 失效
标题翻译：通过改变复位幅度对PCM进行多级单元编程
公开(公告)号：US07944740B2
公开(公告)日：2011-05-17
申请号：US12564904
申请日：2009-09-22
申请人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
发明人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.
摘要翻译：相变存储器件及其编程方法。该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。该方法包括确定用于相变存储器件的特征化的RESET电流斜率。该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

10. 发明申请

US20110069538A1 MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE 失效
标题翻译：通过改变复位电压，PCM的多级电容编程
公开(公告)号：US20110069538A1
公开(公告)日：2011-03-24
申请号：US12564904
申请日：2009-09-22
申请人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
发明人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.
摘要翻译：相变存储器件及其编程方法。该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。该方法包括确定用于相变存储器件的特征化的RESET电流斜率。该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

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