专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07026233B2 Method for reducing defects in post passivation interconnect process 有权
标题翻译：减少后钝化互连过程中的缺陷的方法
公开(公告)号：US07026233B2
公开(公告)日：2006-04-11
申请号：US10635621
申请日：2003-08-06
申请人： Hsi-Kuei Cheng , Hung-Ju Chien , Hsun-Chang Chan , Chu-Chang Chen , Ying-Lang Wang , Chin-Hao Su , Hsien-Ping Feng , Shih-Tzung Chang
发明人： Hsi-Kuei Cheng , Hung-Ju Chien , Hsun-Chang Chan , Chu-Chang Chen , Ying-Lang Wang , Chin-Hao Su , Hsien-Ping Feng , Shih-Tzung Chang
IPC分类号： H01L21/50 , H01L21/44 , H01L21/4763 , H01L21/461
CPC分类号： H01L24/13 , H01L23/3114 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0001 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/18161 , H01L2924/00014
摘要： A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.
摘要翻译：公开了一种形成用于集成电路的后钝化互连的方法。在该集成电路上形成非氧化物材料的钝化层。然后在钝化层上形成缓冲层。缓冲层优选是氧化硅层，其厚度基本上小于钝化层的厚度。在缓冲层上沉积钝化金属层，并且在后钝化金属层中形成连接图案。

2. 发明申请

US20050032353A1 Method for reducing defects in post passivation interconnect process 有权
标题翻译：减少后钝化互连过程中的缺陷的方法
公开(公告)号：US20050032353A1
公开(公告)日：2005-02-10
申请号：US10635621
申请日：2003-08-06
申请人： Hsi-Kuei Cheng , Hung-Ju Chien , Hsun-Chang Chan , Chu-Chang Chen , Ying-Lang Wang , Chin-Hao Su , Hsien-Ping Feng , Shih-Tzung Chang
发明人： Hsi-Kuei Cheng , Hung-Ju Chien , Hsun-Chang Chan , Chu-Chang Chen , Ying-Lang Wang , Chin-Hao Su , Hsien-Ping Feng , Shih-Tzung Chang
IPC分类号： H01L21/4763 , H01L21/60 , H01L23/31 , H01L23/485
CPC分类号： H01L24/13 , H01L23/3114 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0001 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/18161 , H01L2924/00014
摘要： A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.
摘要翻译：公开了一种形成用于集成电路的后钝化互连的方法。在该集成电路上形成非氧化物材料的钝化层。然后在钝化层上形成缓冲层。缓冲层优选是氧化硅层，其厚度基本上小于钝化层的厚度。在缓冲层上沉积钝化金属层，并且在后钝化金属层中形成连接图案。

3. 发明授权

US07528478B2 Semiconductor devices having post passivation interconnections and a buffer layer 有权
标题翻译：具有后钝化互连和缓冲层的半导体器件
公开(公告)号：US07528478B2
公开(公告)日：2009-05-05
申请号：US11363813
申请日：2006-02-28
申请人： Hsi-Kuei Cheng , Hung-Ju Chien , Hsun-Chang Chan , Chu-Chang Chen , Ying-Lang Wang , Chin-Hao Su , Hsien-Ping Feng , Shih-Tzung Chang
发明人： Hsi-Kuei Cheng , Hung-Ju Chien , Hsun-Chang Chan , Chu-Chang Chen , Ying-Lang Wang , Chin-Hao Su , Hsien-Ping Feng , Shih-Tzung Chang
IPC分类号： H01L23/12
CPC分类号： H01L24/13 , H01L23/3114 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0001 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/18161 , H01L2924/00014
摘要： An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.
摘要翻译：公开了具有第二连接图案的后钝化互连的集成电路。在已经具有第一连接图案中的第一多个接触焊盘的集成电路上形成钝化层（优选由非氧化物材料制成）。然后在钝化层上形成缓冲层。缓冲层优选是氧化硅层，其厚度基本上小于钝化层的厚度。后钝化金属层沉积在缓冲层上。作为第二连接图案的一部分的第二多个接触焊盘形成在后钝化金属层中。

4. 发明申请

US20060145332A1 Semiconductor devices having post passivation interconnections with a second connection pattern 有权
标题翻译：具有具有第二连接图案的后钝化互连的半导体器件
公开(公告)号：US20060145332A1
公开(公告)日：2006-07-06
申请号：US11363813
申请日：2006-02-28
申请人： Hsi-Kuei Cheng , Hung-Ju Chien , Hsun-Chang Chan , Chu-Chang Chen , Ying-Lang Wang , Chin-Hao Su , Hsien-Ping Feng , Shih-Tzung Chang
发明人： Hsi-Kuei Cheng , Hung-Ju Chien , Hsun-Chang Chan , Chu-Chang Chen , Ying-Lang Wang , Chin-Hao Su , Hsien-Ping Feng , Shih-Tzung Chang
IPC分类号： H01L23/12
CPC分类号： H01L24/13 , H01L23/3114 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0001 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/18161 , H01L2924/00014
摘要： An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.
摘要翻译：公开了具有第二连接图案的后钝化互连的集成电路。在已经具有第一连接图案中的第一多个接触焊盘的集成电路上形成钝化层（优选由非氧化物材料制成）。然后在钝化层上形成缓冲层。缓冲层优选是氧化硅层，其厚度基本上小于钝化层的厚度。后钝化金属层沉积在缓冲层上。作为第二连接图案的一部分的第二多个接触焊盘形成在后钝化金属层中。

5. 发明授权

US06985222B2 Chamber leakage detection by measurement of reflectivity of oxidized thin film 失效
标题翻译：通过测量氧化薄膜的反射率进行室内泄漏检测
公开(公告)号：US06985222B2
公开(公告)日：2006-01-10
申请号：US10423379
申请日：2003-04-25
申请人： Hsi-Kuei Cheng , Chu-Chang Chen , Ting-Chun Wang , Szu-An Wu , Ying-Lang Wang , Hsien-Ping Feng
发明人： Hsi-Kuei Cheng , Chu-Chang Chen , Ting-Chun Wang , Szu-An Wu , Ying-Lang Wang , Hsien-Ping Feng
IPC分类号： G01N21/88
CPC分类号： G01N21/55 , G01N21/8422 , G01N2201/0227
摘要： A system and method for detecting chamber leakage by measuring the reflectivity of an oxidized thin film. In a preferred embodiment, a method of detecting leaks in a chamber includes providing a first monitor workpiece, placing the first monitor workpiece in the chamber, and forming at least one film on the first monitor workpiece. The reflectivity of the least one film of the first monitor workpiece is measured, wherein the reflectivity indicates whether there are leaks in the at least one seal of the chamber. In another embodiment, the method includes providing a second monitor workpiece, placing the second monitor workpiece in the chamber, and forming at least one film on the second monitor workpiece. The reflectivity of the at least one film of the second monitor workpiece is measured, and the second monitor workpiece film reflectivity is compared to the first monitor workpiece film reflectivity.
摘要翻译：通过测量氧化薄膜的反射率来检测室泄漏的系统和方法。在优选实施例中，检测腔室泄漏的方法包括提供第一监测工件，将第一监测器工件放置在腔室中，以及在第一监测器工件上形成至少一个膜。测量第一监视器工件的至少一个膜的反射率，其中反射率指示在室的至少一个密封件中是否有泄漏。在另一个实施例中，该方法包括提供第二监视器工件，将第二监视器工件放置在腔室中，以及在第二监视器工件上形成至少一个膜。测量第二监测工件的至少一个膜的反射率，并将第二监测工件膜反射率与第一监测工件膜反射率进行比较。

6. 发明授权

US06863491B2 Catch-pin water support for process chamber 失效
标题翻译：捕捉针水处理室支撑
公开(公告)号：US06863491B2
公开(公告)日：2005-03-08
申请号：US10339691
申请日：2003-01-08
申请人： Hsi-Kuei Cheng , Chun-Tse Lin , Ting-Chun Wang , Yu-Ku Lin , Ying-Lang Wang
发明人： Hsi-Kuei Cheng , Chun-Tse Lin , Ting-Chun Wang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/687 , B23B31/16
CPC分类号： H01L21/68707 , Y10T279/1033 , Y10T279/1291 , Y10T279/19
摘要： A new and improved wafer support for supporting wafers in a process chamber such as an edge bead removal (EBR) chamber. The wafer support comprises multiple wafer support units each including a gripper block that engages an edge portion or bevel of the wafer. The gripper block is attached to an engaging and disengaging mechanism for selectively causing engagement of the gripper blocks with the wafer to support the wafer and disengagement of the gripper blocks from the wafer to release the wafer for removal of the wafer from the chamber. The gripper blocks contact little or none of the surface area on the patterned surface of the wafer to prevent or substantially reduce the formation of contact-induced defects on the wafer.
摘要翻译：一种新的和改进的晶片支撑件，用于在诸如边缘珠去除（EBR）室的处理室中支撑晶片。晶片支撑件包括多个晶片支撑单元，每个晶片支撑单元包括接合晶片的边缘部分或斜面的夹持块。夹持块附接到接合和分离机构，用于选择性地使夹持器块与晶片接合以支撑晶片，并且将夹持器块与晶片分离，以释放晶片以从晶片移除。夹持器块几乎不接触晶片的图案化表面上的表面积，以防止或基本上减少晶片上接触引起的缺陷的形成。

7. 发明授权

US06585826B2 Semiconductor wafer cleaning method to remove residual contamination including metal nitride particles 有权
标题翻译：半导体晶片清洗方法去除残留污染物，包括金属氮化物颗粒
公开(公告)号：US06585826B2
公开(公告)日：2003-07-01
申请号：US10000891
申请日：2001-11-02
申请人： Yali Tai , Shih-Chi Lin , Wen-Long Lee , Francis Wang , Szu-An Wu , Hsi-Kuei Cheng , Ying-Lang Wang
发明人： Yali Tai , Shih-Chi Lin , Wen-Long Lee , Francis Wang , Szu-An Wu , Hsi-Kuei Cheng , Ying-Lang Wang
IPC分类号： C23G102
CPC分类号： H01L21/02063 , B08B1/00 , B08B3/04 , B08B3/12 , C11D7/265 , C11D11/0047 , H01L21/02074 , H01L21/67046 , H01L21/67057 , H01L21/67086 , Y10S134/902
摘要： A method of removing residual contamination including metal nitride particles from semiconductor wafer surfaces including the steps of: providing at least one semiconductor wafer with metal nitride particles adhering to the at least one semiconductor wafer surface thereto; subjecting the at least one semiconductor wafer to at least one mechanical brushing process while a cleaning solution including a carboxylic acid is supplied to at least one semiconductor wafer surface; and, subjecting the at least one semiconductor wafer to an a sonic cleaning process including the carboxylic acid cleaning solution.
摘要翻译：一种从半导体晶片表面去除包括金属氮化物颗粒的残留污染的方法，包括以下步骤：向至少一个半导体晶片提供附着在至少一个半导体晶片表面上的金属氮化物颗粒; 使至少一个半导体晶片进行至少一个机械刷洗过程，同时将包含羧酸的清洁溶液供应到至少一个半导体晶片表面; 以及对所述至少一个半导体晶片进行包括所述羧酸清洁溶液的声波清洁处理。

8. 发明申请

US20050275941A1 Metal-filled openings for submicron devices and methods of manufacture thereof 有权
标题翻译：用于亚微米器件的金属填充开口及其制造方法
公开(公告)号：US20050275941A1
公开(公告)日：2005-12-15
申请号：US10854061
申请日：2004-05-26
申请人： Chi-Wen Liu , Jung-Chih Tsao , Shih-Tzung Chang , Ying-Lang Wang , Kei-Wei Chen
发明人： Chi-Wen Liu , Jung-Chih Tsao , Shih-Tzung Chang , Ying-Lang Wang , Kei-Wei Chen
IPC分类号： G02B23/00 , H01L21/768 , H01L21/82
CPC分类号： H01L21/7684 , H01L21/76877
摘要： A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.
摘要翻译：在半导体或其他亚微米器件衬底中形成填充金属的开口的方法包括在衬底表面和开口中形成导电体层，其中导电体层具有第一晶粒尺寸。导电盖层形成在导电体层之上，导电盖层具有基本上小于第一晶粒尺寸的第二晶粒尺寸。导电体和盖层中的至少一个然后被平坦化以形成基本上与衬底表面重合的平坦表面。

9. 发明授权

US07128821B2 Electropolishing method for removing particles from wafer surface 有权
标题翻译：从晶片表面去除颗粒的电抛光方法
公开(公告)号：US07128821B2
公开(公告)日：2006-10-31
申请号：US10761477
申请日：2004-01-20
申请人： Shih-Ho Lin , Chung-Chang Chen , Kei-Wei Chen , Shih-Tzung Chang , Chao-Lung Chen , Po-Jen Shih , Yu-Ku Lin , Ying-Lang Wang
发明人： Shih-Ho Lin , Chung-Chang Chen , Kei-Wei Chen , Shih-Tzung Chang , Chao-Lung Chen , Po-Jen Shih , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： C25D5/34 , C25F1/00
CPC分类号： H01L21/76843 , B24B37/042 , B24B37/046 , C25D3/38 , C25D5/18 , C25D7/123 , C25F3/02 , H01L21/02068 , H01L21/32115 , H01L21/76865 , H01L21/76873
摘要： An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 μm.
摘要翻译：公开了一种用于从晶片去除潜在的器件污染颗粒的电抛光方法。该方法包括将晶片浸入电解抛光电解质溶液中，并通过晶片和电解质溶液之间的旋转摩擦与电解结合从晶片去除缺陷和颗粒。该方法有效地从各种尺寸的通孔开口去除颗粒，包括宽度小于约0.2μm的通孔。

10. 发明申请

US20060055928A1 Test device and method for laser alignment calibration 有权
标题翻译：用于激光对准校准的测试装置和方法
公开(公告)号：US20060055928A1
公开(公告)日：2006-03-16
申请号：US10942554
申请日：2004-09-15
申请人： Shih-Tzung Chang , Yu-Ku Lin , Shih-Ho Lin , Kei-Wei Chen , Ting-Chun Wang , Ching-Hwan Su , Ying-Lang Wang
发明人： Shih-Tzung Chang , Yu-Ku Lin , Shih-Ho Lin , Kei-Wei Chen , Ting-Chun Wang , Ching-Hwan Su , Ying-Lang Wang
IPC分类号： G01B11/00
CPC分类号： H01L22/34 , G01B21/042
摘要： A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.
摘要翻译：一种用于校准从激光计量工具发射的激光束相对于衬底上的目标区域的对准的新型测试装置和方法。测试装置包括具有包括目标点的校准图案的激光敏感材料。当工具被正确调整时，激光束撞击目标点并释放到生产中。如果激光束错过目标点，则重新调整工具并重新测试直到激光束撞击目标点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式