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1. 发明申请

US20080266958A1 FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖板的非易失性记忆体的闪存存储阵列
公开(公告)号：US20080266958A1
公开(公告)日：2008-10-30
申请号：US11861102
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C16/04
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

2. 发明申请

US20100149879A1 FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖板的非易失性记忆体的闪存存储阵列
公开(公告)号：US20100149879A1
公开(公告)日：2010-06-17
申请号：US12711520
申请日：2010-02-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C16/04
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

3. 发明授权

US07688627B2 Flash memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的闪存阵列
公开(公告)号：US07688627B2
公开(公告)日：2010-03-30
申请号：US11861102
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

4. 发明授权

US08345488B2 Flash memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的闪存阵列
公开(公告)号：US08345488B2
公开(公告)日：2013-01-01
申请号：US13080814
申请日：2011-04-06
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C16/04
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

5. 发明申请

US20110182126A1 FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖板的非易失性记忆体的闪存存储阵列
公开(公告)号：US20110182126A1
公开(公告)日：2011-07-28
申请号：US13080814
申请日：2011-04-06
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C16/16
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

6. 发明授权

US07944745B2 Flash memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的闪存阵列
公开(公告)号：US07944745B2
公开(公告)日：2011-05-17
申请号：US12711520
申请日：2010-02-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Prabhjot Singh , Michael D. Church
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0416
摘要： A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：闪存阵列包括以行和列的矩阵组织的多个存储单元。每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。多个字线各自电连接到相应行中的每个存储器单元中的电容器。第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。多个高压存取晶体管分别电连接到第一组位线中的位线。第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

7. 发明授权

US07903465B2 Memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的存储器阵列
公开(公告)号：US07903465B2
公开(公告)日：2011-03-08
申请号：US11861111
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/06 , G11C16/10 , G11C16/12
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

8. 发明授权

US08325522B2 Memory array of floating gate-based non-volatile memory cells 有权
标题翻译：基于浮动栅极的非易失性存储单元的存储器阵列
公开(公告)号：US08325522B2
公开(公告)日：2012-12-04
申请号：US13012361
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

9. 发明申请

US20080266959A1 MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖帽的不挥发性记忆细胞的记忆阵列
公开(公告)号：US20080266959A1
公开(公告)日：2008-10-30
申请号：US11861111
申请日：2007-09-25
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

10. 发明申请

US20110116324A1 MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
标题翻译：基于盖帽的不挥发性记忆细胞的记忆阵列
公开(公告)号：US20110116324A1
公开(公告)日：2011-05-19
申请号：US13012368
申请日：2011-01-24
申请人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
发明人： Hosam Haggag , Alexander Kalnitsky , Edgardo Laber , Michael D. Church , Yun Yue
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.
摘要翻译：存储器阵列包括以行和列的矩阵组织的多个存储器单元。每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。第一组字线分别电连接到相应行中的每个存储器单元中的电容器。第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

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