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    • 9. 发明授权
    • Synchronous semiconductor memory having an improved reading margin and an improved timing control in a test mode
    • 同步半导体存储器具有改进的读取余量和改进的测试模式中的定时控制
    • US06208583B1
    • 2001-03-27
    • US09430298
    • 1999-10-29
    • Keisuke Fujiwara
    • Keisuke Fujiwara
    • G11C800
    • G11C7/1069G11C7/06G11C7/1051G11C7/1072G11C2207/108
    • A synchronous semiconductor memory comprises a memory controller receiving a pre-CAS signal and a test-CAS signal for outputting the test-CAS signal as the CAS signal when a mode discrimination signal is active to indicate a test mode, and the pre-CAS signal as the CAS signal when the mode discrimination signal is inactive. A data amplifier controller receives the CAS signal and a clock signal and generates a data amplifier enable signal in time with the clock signal when the mode discrimination signal is inactive. This data amplifier control generates the data amplifier enable signal by delaying the CAS signal when the mode discrimination signal is inactive. In response to a column selection signal, data stored in the memory cell array is outputted to associated data amplifiers. When the associated data amplifiers are enabled by the data amplifier enable signal, the data outputted from the memory cell array is amplified and outputted by the associated data amplifiers.
    • 同步半导体存储器包括存储器控制器,当模式识别信号有效以指示测试模式时,接收预先CAS信号和测试CAS信号,用于输出测试CAS信号作为CAS信号,并且前置CAS信号 作为模式识别信号无效时的CAS信号。 数据放大器控制器接收CAS信号和时钟信号,并且当模式鉴别信号无效时,随时钟信号及时产生数据放大器使能信号。 当模式识别信号无效时,该数据放大器控制通过延迟CAS信号来产生数据放大器使能信号。 响应于列选择信号,存储在存储单元阵列中的数据被输出到相关联的数据放大器。 当相关的数据放大器由数据放大器使能信号使能时,从存储单元阵列输出的数据被相关的数据放大器放大并输出。