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    • 2. 发明授权
    • Active snubber for synchronous rectifier
    • 用于同步整流器的主动缓冲器
    • US06771521B1
    • 2004-08-03
    • US10371449
    • 2003-02-20
    • Yahong XiongZhongwei KeAlpha J. Zhang
    • Yahong XiongZhongwei KeAlpha J. Zhang
    • H02H7125
    • H02M1/34H02M3/33592H02M2001/342Y02B70/1475Y02B70/1491
    • The invention relates to an active snubber for synchronous rectifier. The active snubber is coupled across a synchronous rectifier having a first synchronous MOSFET and a second synchronous MOSFET coupled to a transformer in a power converter. The active snubber includes a series-coupled active switch and first snubber capacitor which is coupled between a drain terminal and a source terminal of the first synchronous MOSFET, a gate driver operative to keep the active switch conducting a specified period of time during a non-conduction interval of the first synchronous MOSFET. The gate driver is composed of an auxiliary winding, a capacitor, and a resistor, wherein the auxiliary winding and the capacitor are connected in series and then coupled across the resistor in parallel, which is coupled between a gate and a source of the active switch.
    • 本发明涉及用于同步整流器的有源缓冲器。 有源缓冲器耦合在同步整流器上,该同步整流器具有耦合到功率转换器中的变压器的第一同步MOSFET和第二同步MOSFET。 有源缓冲器包括耦合在第一同步MOSFET的漏极端子和源极端子之间的串联耦合的有源开关和第一缓冲电容器,栅极驱动器可操作以使有源开关在非易失性存储器中保持特定的时间段, 第一同步MOSFET的导通间隔。 栅极驱动器由辅助绕组,电容器和电阻器组成,其中辅助绕组和电容器串联连接,然后并联耦合在电阻器两端,耦合在有源开关的栅极和源极之间 。
    • 4. 发明授权
    • Driving circuit for DC/DC converter
    • DC / DC转换器的驱动电路
    • US07006364B2
    • 2006-02-28
    • US10801899
    • 2004-03-15
    • Bin JinZhongwei KeYahong XiongAlpha J. Zhang
    • Bin JinZhongwei KeYahong XiongAlpha J. Zhang
    • H02M3/335
    • H02M1/34H02M1/08H02M3/335H02M2001/342Y02B70/1491
    • A driving circuit comprises an input terminal receiving an input of a PWM signal, a first output terminal connected to a main switch for outputting a low-side driving signal, a second output terminal connected to an active switch for outputting a high-side driving signal, a first branch having a voltage level shifting capacitor and a first buffer connected in series between the input terminal and the second output terminal; and a second branch having a delay circuit and a second buffer connected in series between the input terminal and the first output terminal. When the input of the PWM signal turns from a low level to a high level, the voltage level shifting capacitor transmits the input of PWM signal to the first buffer for turning off the active switch and then triggering the second buffer to turn on the main switch with a short time delay.
    • 驱动电路包括接收PWM信号的输入的输入端子,连接到用于输出低侧驱动信号的主开关的第一输出端子,连接到用于输出高侧驱动信号的有源开关的第二输出端子 ,具有电压电平移位电容器和在所述输入端子和所述第二输出端子之间串联连接的第一缓冲器的第一分支; 以及第二分支,具有在输入端子和第一输出端子之间串联连接的延迟电路和第二缓冲器。 当PWM信号的输入从低电平变为高电平时,电压电平移位电容器将PWM信号的输入发送到第一缓冲器,用于关断有源开关,然后触发第二缓冲器以接通主开关 短时间延迟。
    • 5. 发明授权
    • Isolated voltage regulator with one core structure
    • 隔离式电压调节器,具有一个核心结构
    • US06853568B2
    • 2005-02-08
    • US10441620
    • 2003-05-20
    • Wenhua LiZhongwei KeGuisong HuangAlpha J. Zhang
    • Wenhua LiZhongwei KeGuisong HuangAlpha J. Zhang
    • H02M3/335
    • H02M3/33592Y02B70/1475
    • The present invention proposes a new structure for a high input VRM. This structure is similar to a simple buck converter and can simplify the 48V input VRM design. In this present invention, the interleaved voltage regulator is provided. The interleaved voltage regulator includes an integrated magnetic device for performing both transformer and output choke filter function, a first switch, a second switch, a third switch, and a fourth switch, wherein the integrated magnetic device includes a transformer having a first primary winding, a second primary winding, a first secondary winding, and a second secondary winding, a first choke filter having one end coupled to a first terminal of the first secondary winding, and a second choke filter having one end coupled to a first terminal of the second secondary winding, and the other end of the second choke filter coupled to the other end of the first choke filter to form the output terminal of the isolated voltage regulator. The first switch, the second switch, the first choke filter, and the first secondary winding form a synchronous rectifier circuit. The third switch, the fourth switch, the second choke filter, and the second secondary winding form another synchronous rectifier circuit.
    • 本发明提出了一种高输入VRM的新结构。 这种结构类似于简单的降压转换器,可以简化48V输入VRM设计。 在本发明中,提供了交错式电压调节器。 交错式电压调节器包括用于执行变压器和输出扼流圈滤波器功能的集成磁性装置,第一开关,第二开关,第三开关和第四开关,其中所述集成磁性装置包括具有第一初级绕组的变压器, 第二初级绕组,第一次级绕组和第二次级绕组,第一扼流器滤波器,其一端耦合到第一次级绕组的第一端子,以及第二扼流器滤波器,其一端耦合到第二次级绕组的第一端子 次级绕组,并且第二扼流圈滤波器的另一端耦合到第一扼流圈滤波器的另一端,以形成隔离稳压器的输出端。 第一开关,第二开关,第一扼流圈滤波器和第一次级绕组形成同步整流电路。 第三开关,第四开关,第二扼流圈滤波器和第二次级绕组形成另一同步整流电路。
    • 6. 发明授权
    • Energy storage circuit for DC-DC converter
    • 用于DC-DC转换器的储能电路
    • US06538906B1
    • 2003-03-25
    • US10074074
    • 2002-02-11
    • Zhongwei KeAlpha J. ZhangBin Jin
    • Zhongwei KeAlpha J. ZhangBin Jin
    • H02M3335
    • H02M3/33569H02J9/061
    • An energy storage circuit for a wide input voltage range DC-DC converter with holdup time requirement. The energy storage circuit comprises (1) an energy storage capacitor, (2) a charging path including a diode connected in series with a current limiting resistor coupled in series with the energy storage capacitor, (3) a discharging path including a parallel-coupled switch and a diode coupled in series with a filtering inductor which is coupled in series with the energy storage capacitor, and (4) a logic control unit coupled to the switch for turning the switch of the discharge path on and off.
    • 一种用于宽输入电压范围DC-DC转换器的储能电路,具有保持时间要求。 能量存储电路包括(1)储能电容器,(2)充电路径,其包括与与所述储能电容器串联耦合的限流电阻器串联的二极管,(3)放电路径,包括并联耦合 开关和与与能量存储电容器串联耦合的滤波电感器串联耦合的二极管,以及(4)耦合到开关的逻辑控制单元,用于打开和关闭放电路径的开关。
    • 7. 发明申请
    • Driving circuit for DC/DC converter
    • DC / DC转换器的驱动电路
    • US20050201128A1
    • 2005-09-15
    • US10801899
    • 2004-03-15
    • Bin JinZhongwei KeYahong XiongAlpha Zhang
    • Bin JinZhongwei KeYahong XiongAlpha Zhang
    • H02H7/122
    • H02M1/34H02M1/08H02M3/335H02M2001/342Y02B70/1491
    • A driving circuit comprises an input terminal receiving an input of a PWM signal, a first output terminal connected to a main switch for outputting a low-side driving signal, a second output terminal connected to an active switch for outputting a high-side driving signal, a first branch having a voltage level shifting capacitor and a first buffer connected in series between the input terminal and the second output terminal; and a second branch having a delay circuit and a second buffer connected in series between the input terminal and the first output terminal. When the input of the PWM signal turns from a low level to a high level, the voltage level shifting capacitor transmits the input of PWM signal to the first buffer for turning off the active switch and then triggering the second buffer to turn on the main switch with a short time delay.
    • 驱动电路包括接收PWM信号的输入的输入端子,连接到用于输出低侧驱动信号的主开关的第一输出端子,连接到用于输出高侧驱动信号的有源开关的第二输出端子 ,具有电压电平移位电容器和在所述输入端子和所述第二输出端子之间串联连接的第一缓冲器的第一分支; 以及第二分支,具有在输入端子和第一输出端子之间串联连接的延迟电路和第二缓冲器。 当PWM信号的输入从低电平变为高电平时,电压电平移位电容器将PWM信号的输入发送到第一缓冲器,用于关断有源开关,然后触发第二缓冲器以接通主开关 短时间延迟。