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1. 发明申请

US20140061732A1 METHOD AND DEVICE TO ACHIEVE SELF-STOP AND PRECISE GATE HEIGHT 有权
标题翻译：实现自停和精确门高度的方法和设备
公开(公告)号：US20140061732A1
公开(公告)日：2014-03-06
申请号：US13596808
申请日：2012-08-28
申请人： Hong Yu , Wang Haiting , Yongsik Moon , James Lee , Huang Liu
发明人： Hong Yu , Wang Haiting , Yongsik Moon , James Lee , Huang Liu
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/165 , H01L21/76837 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A method for enabling fabrication of RMG devices having a low gate height variation and a substantially planar topography and resulting device are disclosed. Embodiments include: providing on a substrate two dummy gate electrodes, each between a pair of spacers; providing a source/drain region between the two dummy gate electrodes; and forming a first nitride layer over the two dummy gate electrodes and the source/drain region, wherein the first nitride layer comprises a first portion over the dummy gate electrodes and a second portion over the source/drain region, and the second portion has an upper surface substantially coplanar with an upper surface of the dummy gate electrodes.
摘要翻译：公开了一种能够制造具有低栅极高度变化的RMG器件和基本平坦的地形和结果器件的方法。实施例包括：在衬底上提供两个虚拟栅极电极，每个在一对间隔物之间; 在两个虚拟栅电极之间提供源/漏区; 以及在所述两个伪栅极电极和所述源极/漏极区域上形成第一氮化物层，其中所述第一氮化物层包括在所述伪栅极电极之上的第一部分和所述源极/漏极区域上的第二部分，并且所述第二部分具有上表面与虚拟栅电极的上表面基本上共面。

2. 发明授权

US08962407B2 Method and device to achieve self-stop and precise gate height 有权
标题翻译：实现自动，精确门高的方法和装置
公开(公告)号：US08962407B2
公开(公告)日：2015-02-24
申请号：US13596808
申请日：2012-08-28
申请人： Hong Yu , Wang Haiting , Yongsik Moon , James Lee , Huang Liu
发明人： Hong Yu , Wang Haiting , Yongsik Moon , James Lee , Huang Liu
IPC分类号： H01L21/338
CPC分类号： H01L29/165 , H01L21/76837 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A method for enabling fabrication of RMG devices having a low gate height variation and a substantially planar topography and resulting device are disclosed. Embodiments include: providing on a substrate two dummy gate electrodes, each between a pair of spacers; providing a source/drain region between the two dummy gate electrodes; and forming a first nitride layer over the two dummy gate electrodes and the source/drain region, wherein the first nitride layer comprises a first portion over the dummy gate electrodes and a second portion over the source/drain region, and the second portion has an upper surface substantially coplanar with an upper surface of the dummy gate electrodes.
摘要翻译：公开了一种能够制造具有低栅极高度变化的RMG器件和基本平坦的地形和结果器件的方法。实施例包括：在衬底上提供两个虚拟栅极电极，每个在一对间隔物之间; 在两个虚拟栅电极之间提供源/漏区; 以及在所述两个伪栅极电极和所述源极/漏极区域上形成第一氮化物层，其中所述第一氮化物层包括在所述伪栅极电极之上的第一部分和所述源极/漏极区域上的第二部分，并且所述第二部分具有上表面与虚拟栅电极的上表面基本上共面。

3. 发明授权

US08519482B2 Reliable contacts 有权
标题翻译：可靠的联系人
公开(公告)号：US08519482B2
公开(公告)日：2013-08-27
申请号：US13246879
申请日：2011-09-28
申请人： Hong Yu , Huang Liu
发明人： Hong Yu , Huang Liu
IPC分类号： H01L21/70
CPC分类号： H01L29/4175 , H01L21/76814 , H01L21/7682 , H01L21/76897 , H01L21/823425 , H01L21/823475 , Y10S438/957
摘要： A method for forming a device is disclosed. The method includes providing a substrate prepared with first and second contact regions and a dielectric layer over the contact region. First and second vias are formed in the dielectric layer. The first via is in communication with the first contact region and the second via is in communication with the second contact region. A buried void provides a communication path between the first and second vias. The vias and buried void are at least partially filled with a dielectric filler. The partially filled buried void blocks the communication path between the first and second vias created by the buried void. The dielectric filler in the vias is removed, leaving remaining dielectric filler in the buried void to block the communication path between the first and second vias and contact plugs are formed in the vias.
摘要翻译：公开了一种用于形成装置的方法。该方法包括提供用第一和第二接触区域制备的衬底和在接触区域上的电介质层。第一和第二通孔形成在电介质层中。第一通孔与第一接触区域连通，第二通孔与第二接触区域连通。埋置的空隙提供第一和第二通孔之间的连通路径。通孔和掩埋的空隙至少部分地填充有介电填料。部分填充的掩埋空隙阻挡由埋入空隙产生的第一和第二通孔之间的连通路径。去除通孔中的介电填料，留下掩埋空隙中的剩余电介质填料阻止第一和第二通孔之间的连通路径，并且在通孔中形成接触塞。

4. 发明授权

US08962474B2 Method for forming an air gap around a through-silicon via 有权
标题翻译：在通过硅通孔周围形成气隙的方法
公开(公告)号：US08962474B2
公开(公告)日：2015-02-24
申请号：US13290791
申请日：2011-11-07
申请人： Hong Yu , Huang Liu
发明人： Hong Yu , Huang Liu
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48
CPC分类号： H01L23/481 , H01L21/7682 , H01L21/76898 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices with air gaps around the through-silicon via are formed. Embodiments include forming a first cavity in a substrate, filling the first cavity with a sacrificial material, forming a second cavity in the substrate, through the sacrificial material, by removing a portion of the sacrificial material and a portion of the substrate below the sacrificial material, filling the second cavity with a conductive material, removing a remaining portion of the sacrificial material to form an air gap between the conductive material and the substrate, and forming a cap over the air gap.
摘要翻译：形成具有穿过硅通孔的气隙的半导体器件。实施例包括在衬底中形成第一腔，用牺牲材料填充第一腔，通过牺牲材料在衬底中形成第二腔，通过去除牺牲材料的一部分和牺牲材料下方的一部分衬底用导电材料填充第二腔，去除牺牲材料的剩余部分以在导电材料和衬底之间形成气隙，并在气隙上形成帽。

5. 发明授权

US08883634B2 Package interconnects 有权
标题翻译：封装互连
公开(公告)号：US08883634B2
公开(公告)日：2014-11-11
申请号：US13171478
申请日：2011-06-29
申请人： Hong Yu , Huang Liu
发明人： Hong Yu , Huang Liu
IPC分类号： H01L21/28 , H01L21/768 , B81B3/00 , H01L23/48
CPC分类号： H01L23/5226 , B81B3/0072 , B81B2207/015 , B81B2207/07 , H01L21/76831 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a device is disclosed. A substrate having first and second major surfaces is provided. A stress buffer is formed in the substrate. A through silicon via (TSV) contact is formed between the stress buffer. The stress buffer has a depth less than a depth of the TSV contact. The stress buffer alleviates stress created by the difference in coefficient thermal expansion (CTE) between the TSV contact and the substrate.
摘要翻译：公开了一种用于形成装置的方法。提供具有第一和第二主表面的基板。在衬底中形成应力缓冲器。在应力缓冲器之间形成贯通硅通孔（TSV）接触。应力缓冲器的深度小于TSV接触深度。应力缓冲器减轻由TSV接触和基板之间的系数热膨胀差（CTE）产生的应力。

6. 发明申请

US20130069232A1 DAMASCENE PROCESS FOR ALIGNING AND BONDING THROUGH-SILICON-VIA BASED 3D INTEGRATED CIRCUIT STACKS 有权
标题翻译：用于通过基于硅的三维集成电路堆栈进行对准和结合的大金刚石工艺
公开(公告)号：US20130069232A1
公开(公告)日：2013-03-21
申请号：US13234405
申请日：2011-09-16
申请人： Hong Yu , Huang Liu
发明人： Hong Yu , Huang Liu
IPC分类号： H01L23/522 , H01L21/60
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06541 , H01L2924/1461 , H01L2924/00
摘要： Through-silicon-via (TSV) based 3D integrated circuit (3D IC) stacks are aligned, bonded and electrically interconnected using a transparent alignment material in the TSVs until the wafers are bonded. Embodiments include providing a first wafer having a first device layer and at least one first TSV filled with a conductive material, providing a second wafer having a second device layer, forming at least one second TSV in the second wafer, filling each second TSV with an alignment material, thinning the second wafer until the transparent material extends all the way through the wafer, aligning the first and second wafers, bonding the first and second wafers, removing the alignment material from the second wafer, and filling each second TSV in the second wafer with a conductive material.
摘要翻译：基于硅通孔（TSV）的3D集成电路（3D IC）堆叠使用TSV中的透明对准材料进行对准，电连接并电连接，直到晶片结合为止。实施例包括提供具有第一器件层的第一晶片和填充有导电材料的至少一个第一TSV，提供具有第二器件层的第二晶片，在第二晶片中形成至少一个第二TSV，用第对准材料，使第二晶片变薄直到透明材料一直延伸穿过晶片，对准第一和第二晶片，结合第一和第二晶片，从第二晶片去除对准材料，并将第二TSV填充在第二晶片中晶圆与导电材料。

7. 发明授权

US08877637B2 Damascene process for aligning and bonding through-silicon-via based 3D integrated circuit stacks 有权
标题翻译：用于对准和粘合通过硅通孔的3D集成电路堆叠的镶嵌工艺
公开(公告)号：US08877637B2
公开(公告)日：2014-11-04
申请号：US13234405
申请日：2011-09-16
申请人： Hong Yu , Huang Liu
发明人： Hong Yu , Huang Liu
IPC分类号： H01L21/44 , H01L21/16 , H01L21/30 , H01L21/46 , H01L25/00 , H01L25/065 , H01L21/768
CPC分类号： H01L21/76898 , H01L25/0657 , H01L25/50 , H01L2224/16 , H01L2225/06541 , H01L2924/1461 , H01L2924/00
摘要： Through-silicon-via (TSV) based 3D integrated circuit (3D IC) stacks are aligned, bonded and electrically interconnected using a transparent alignment material in the TSVs until the wafers are bonded. Embodiments include providing a first wafer having a first device layer and at least one first TSV filled with a conductive material, providing a second wafer having a second device layer, forming at least one second TSV in the second wafer, filling each second TSV with an alignment material, thinning the second wafer until the transparent material extends all the way through the wafer, aligning the first and second wafers, bonding the first and second wafers, removing the alignment material from the second wafer, and filling each second TSV in the second wafer with a conductive material.
摘要翻译：基于硅通孔（TSV）的3D集成电路（3D IC）堆叠使用TSV中的透明对准材料进行对准，电连接并电连接，直到晶片结合为止。实施例包括提供具有第一器件层的第一晶片和填充有导电材料的至少一个第一TSV，提供具有第二器件层的第二晶片，在第二晶片中形成至少一个第二TSV，用第对准材料，使第二晶片变薄直到透明材料一直延伸穿过晶片，对准第一和第二晶片，结合第一和第二晶片，从第二晶片去除对准材料，并将第二TSV填充在第二晶片中晶圆与导电材料。

8. 发明申请

US20110316166A1 INTEGRATED CIRCUIT SYSTEM WITH VIA AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：集成电路系统及其制造方法
公开(公告)号：US20110316166A1
公开(公告)日：2011-12-29
申请号：US12825266
申请日：2010-06-28
申请人： Hong Yu , Huang Liu , Feng Zhao , Meisheng Zhou , Liang-Choo Hsia
发明人： Hong Yu , Huang Liu , Feng Zhao , Meisheng Zhou , Liang-Choo Hsia
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/7684
摘要： A method of manufacture of an integrated circuit system includes: forming an etch stop layer over a bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a through silicon via through the etch stop layer with the hard mask detected and the buffer layer removed with a low down force; and forming a passivation layer on the through silicon via and the etch stop layer.
摘要翻译：集成电路系统的制造方法包括：在体基板上形成蚀刻停止层; 在所述蚀刻停止层上形成缓冲层; 在缓冲层上形成硬掩模; 通过所述蚀刻停止层形成穿透硅通孔，所述硬掩模被检测并且所述缓冲层以低的下压力去除; 以及在穿通硅通孔和蚀刻停止层上形成钝化层。

9. 发明授权

US08405222B2 Integrated circuit system with via and method of manufacture thereof 有权
标题翻译：集成电路系统及其制造方法
公开(公告)号：US08405222B2
公开(公告)日：2013-03-26
申请号：US12825266
申请日：2010-06-28
申请人： Hong Yu , Huang Liu , Feng Zhao , Meisheng Zhou , Liang-Choo Hsia
发明人： Hong Yu , Huang Liu , Feng Zhao , Meisheng Zhou , Liang-Choo Hsia
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L21/7684
摘要： A method of manufacture of an integrated circuit system includes: forming an etch stop layer over a bulk substrate; forming a buffer layer on the etch stop layer; forming a hard mask on the buffer layer; forming a through silicon via through the etch stop layer with the hard mask detected and the buffer layer removed with a low down force; and forming a passivation layer on the through silicon via and the etch stop layer.
摘要翻译：集成电路系统的制造方法包括：在体基板上形成蚀刻停止层; 在所述蚀刻停止层上形成缓冲层; 在缓冲层上形成硬掩模; 通过所述蚀刻停止层形成穿透硅通孔，所述硬掩模被检测并且所述缓冲层以低的下压力去除; 以及在穿通硅通孔和蚀刻停止层上形成钝化层。

10. 发明申请

US20190196448A1 Method for Simulating Daylight Performance of Buildings Based on Regional Daylight Climate Data 审中-公开
公开(公告)号：US20190196448A1
公开(公告)日：2019-06-27
申请号：US16010497
申请日：2018-06-17
申请人： Cheng Sun , Yunsong Han , Ying Zi , Dagang Qu , Yongheng Jia , Lei Liu , Hong Yu
发明人： Cheng Sun , Yunsong Han , Ying Zi , Dagang Qu , Yongheng Jia , Lei Liu , Hong Yu
IPC分类号： G05B19/4099 , B33Y50/02
摘要： The present invention provides a method for simulating daylight performance of buildings based on regional daylight climate data. The method comprises the steps of: establishing a regional sky luminance distribution database from measured data; mapping sky luminance data to an artificial sky lamp group; using a 3D printing machine to fabricate a scaled physical model based on real parameters of the building to be simulated; and using the scaled physical model in the artificial sky integrated with regional sky luminance distribution data to make the daylight performance simulation. This method can achieve high-precision simulation of the daylight performance of buildings by using regional sky daylight climate data with a highly accurate physical model of the building.

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