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1. 发明授权

US07990235B1 Simultaneous switching noise filter architecture and method 有权
标题翻译：同时开关噪声滤波器架构与方法
公开(公告)号：US07990235B1
公开(公告)日：2011-08-02
申请号：US12128581
申请日：2008-05-28
申请人： Yee Huan Yew , Hong Shi
发明人： Yee Huan Yew , Hong Shi
IPC分类号： H01P1/203 , H03H7/09
CPC分类号： H01P1/2039
摘要： The present invention is directed to a transmission line assembly and method of propagating signals therethrough that features forming transmission lines of the assembly to provide desired filtering properties. To that end, the assembly includes a plurality of spaced-apart transmission lines placing first and second sets of active circuits in electrical communication, with a subset of the plurality of spaced apart transmission lines having dimensions to filter unwanted characteristics of signals, propagating between the first and second sets and inductively coupled between one or more of the plurality of spaced-apart transmission lines. The method performs the function of the assembly.
摘要翻译：本发明涉及传输线组件和传播信号的方法，其特征在于，形成组件的传输线以提供期望的过滤性能。为此，组件包括多个间隔开的传输线，将第一组和第二组有源电路组置于电气通信中，多个间隔开的传输线的子集具有滤除信号不需要的特性的尺寸，第一和第二组并且感应耦合在所述多个间隔开的传输线中的一个或多个之间。该方法执行装配的功能。

2. 发明授权

US07640523B1 Substrate via patterns for optimal power distribution and manufacturability in semiconductor die packages 有权
标题翻译：基板图案，用于半导体芯片封装中的最佳配电和可制造性
公开(公告)号：US07640523B1
公开(公告)日：2009-12-29
申请号：US11747189
申请日：2007-05-10
申请人： Hong Shi , Yee Huan Yew
发明人： Hong Shi , Yee Huan Yew
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5077
摘要： The embodiments of the present invention provide methods for choosing a via layout pattern(s) for power distribution network in a package for a semiconductor die. The chosen via layout pattern allows the power distribution network to meet the limitation on the loop inductance in order to avoid causing a large ΔV affecting the functionality of semiconductor devices on the die. In addition, the chosen via layout pattern also meets the limitation of total number of vias allowed for the power distribution network in the package.
摘要翻译：本发明的实施例提供了用于选择用于半导体管芯的封装中的用于配电网络的通孔布局图案的方法。所选择的通孔布局模式允许配电网络满足环路电感的限制，以避免导致大的DeltaV影响芯片上的半导体器件的功能。此外，选择的通孔布局模式还满足了封装中配电网络允许的通孔总数的限制。

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