专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070075360A1 Cobalt silicon contact barrier metal process for high density semiconductor power devices 审中-公开
标题翻译：用于高密度半导体功率器件的钴硅接触屏障金属工艺
公开(公告)号：US20070075360A1
公开(公告)日：2007-04-05
申请号：US11240255
申请日：2005-09-30
申请人： Hong Chang , Tiesheng Li , Sung-Shan Tai , Daniel Ng , Anup Bhalla
发明人： Hong Chang , Tiesheng Li , Sung-Shan Tai , Daniel Ng , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/28518 , H01L21/76843 , H01L21/76855 , H01L29/456 , H01L29/4933 , H01L29/4941 , H01L29/66734 , H01L29/7811
摘要： This invention discloses an improved trenched metal oxide semiconductor field effect transistor (MOSFET) cell that includes a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The MOSFET cell further includes a source contact opening opened on top of an area extended over the body region and the source region through a protective insulation layer wherein the area further has a cobalt-silicide layer disposed near a top surface of the substrate. The MOSFET cell further includes a Ti/TiN conductive layer covering the area interfacing with the cobalt-silicide layer over the source contact opening. The MOSFET cell further includes a source contact metal layer formed on top of the Ti/TiN conductive layer ready to form source-bonding wires thereon.
摘要翻译：本发明公开了一种改进的沟槽金属氧化物半导体场效应晶体管（MOSFET）单元，其包括被包围在设置在基板的底表面上的漏极区域上方的体区域中的源极区域包围的沟槽栅极。 MOSFET单元进一步包括源极接触开口，该开口位于通过保护绝缘层延伸到主体区域上的区域的顶部，并且源区域通过保护绝缘层开放，其中该区域还具有设置在基板顶表面附近的硅化钴层。 MOSFET单元还包括覆盖源极接触开口上与硅化钴层接合的区域的Ti / TiN导电层。 MOSFET单元还包括形成在Ti / TiN导电层的顶部上的源极接触金属层，准备在其上形成源极接合线。

2. 发明申请

US20060071268A1 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US20060071268A1
公开(公告)日：2006-04-06
申请号：US10952231
申请日：2004-09-27
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.
摘要翻译：半导体器件包括漏极，与漏极接触的主体，主体具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中，延伸穿过源和主体的沟槽并且设置在沟槽中的门具有大致在主体顶表面上方延伸的门顶表面。一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

3. 发明授权

US07667264B2 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US07667264B2
公开(公告)日：2010-02-23
申请号：US10952231
申请日：2004-09-27
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.
摘要翻译：半导体器件包括漏极，与漏极接触的主体，主体具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中，延伸穿过源和主体的沟槽并且设置在沟槽中的门具有大致在主体顶表面上方延伸的门顶表面。一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

4. 发明申请

US20100105182A1 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US20100105182A1
公开(公告)日：2010-04-29
申请号：US12655162
申请日：2009-12-22
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall. It further includes implanting a body, implanting a plurality of source regions embedded in the body, forming a plurality of spacers that insulate the source regions from the gate, the plurality of spacers being situated immediately adjacent to the gate and immediately adjacent to respective ones of the plurality of source regions, wherein the plurality of spacers do not substantially extend into the trench and do not substantially extend over the trench, disposing a dielectric layer over the source, the spacers, the gate, and at least a portion of the body, forming a contact opening, and disposing metal to form a contact with the body at the contact opening.
摘要翻译：制造半导体器件包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中通过硬掩模形成沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部并且去除硬掩模以离开具有栅极顶表面的栅极，该栅极顶表面至少在沟槽开口的中心区域基本上在顶部衬底表面上方延伸，栅极具有包括延伸部分的垂直边缘，延伸部分延伸到沟槽开口之上并与沟槽壁基本对齐。它还包括植入物体，植入嵌入在体内的多个源区，形成多个间隔物，使得源极区域与栅极绝缘，多个间隔物紧邻栅极并且紧邻栅极所述多个源极区域，其中所述多个间隔物基本上不延伸到所述沟槽中并且基本上不延伸穿过所述沟槽，在所述源极，所述间隔物，所述栅极以及所述主体的至少一部分之间设置介电层，形成接触开口，并且在接触开口处设置金属以与身体形成接触。

5. 发明授权

US08008151B2 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US08008151B2
公开(公告)日：2011-08-30
申请号：US11983769
申请日：2007-11-09
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.
摘要翻译：一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

6. 发明申请

US20080090357A1 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US20080090357A1
公开(公告)日：2008-04-17
申请号：US11983769
申请日：2007-11-09
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.
摘要翻译：一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

7. 发明授权

US07875541B2 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US07875541B2
公开(公告)日：2011-01-25
申请号：US12655162
申请日：2009-12-22
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L21/3205
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall. It further includes implanting a body, implanting a plurality of source regions embedded in the body, forming a plurality of spacers that insulate the source regions from the gate, the plurality of spacers being situated immediately adjacent to the gate and immediately adjacent to respective ones of the plurality of source regions, wherein the plurality of spacers do not substantially extend into the trench and do not substantially extend over the trench, disposing a dielectric layer over the source, the spacers, the gate, and at least a portion of the body, forming a contact opening, and disposing metal to form a contact with the body at the contact opening.
摘要翻译：制造半导体器件包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中通过硬掩模形成沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部并且去除硬掩模以离开具有栅极顶表面的栅极，该栅极顶表面至少在沟槽开口的中心区域基本上在顶部衬底表面上方延伸，栅极具有包括延伸部分的垂直边缘，延伸部分延伸到沟槽开口之上并与沟槽壁基本对齐。它还包括植入物体，植入嵌入在体内的多个源区，形成多个间隔物，使得源极区域与栅极绝缘，多个间隔物紧邻栅极并且紧邻栅极所述多个源极区域，其中所述多个间隔物基本上不延伸到所述沟槽中并且基本上不延伸穿过所述沟槽，在所述源极，所述间隔物，所述栅极以及所述主体的至少一部分之上设置介电层，形成接触开口，并且在接触开口处设置金属以与身体形成接触。

8. 发明申请

US20130093001A1 POWER MOSFET DEVICE STRUCTURE FOR HIGH FREQUENCY APPLICATIONS 有权
标题翻译：功率MOSFET器件结构高频应用
公开(公告)号：US20130093001A1
公开(公告)日：2013-04-18
申请号：US13436192
申请日：2012-03-30
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
IPC分类号： H01L29/78
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface. An insulated gate electrode is disposed on top of the second surface for controlling a source to drain current and a source electrode is interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region, An epitaxial layer is disposed above and having a different dopant concentration than the drain region. The gate electrode is insulated from the source electrode by an insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种新的开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的半导体的第二表面附近的源极区域。绝缘栅电极设置在第二表面的顶部，用于控制源极到漏极电流，并且源电极插入到绝缘栅电极中，用于基本上防止栅极电极和绝缘栅极之间的外延区域之间的电场的耦合栅电极。源极电极进一步覆盖并延伸在绝缘栅上，用于覆盖半导体的第二表面上的区域以接触源极区。外延层设置在漏极区之上并且具有不同掺杂剂浓度。栅极通过具有取决于垂直功率器件的Vgsmax额定值的厚度的绝缘层与源电极绝缘。

9. 发明授权

US08963233B2 Power MOSFET device structure for high frequency applications 有权
标题翻译：功率MOSFET器件结构用于高频应用
公开(公告)号：US08963233B2
公开(公告)日：2015-02-24
申请号：US13436192
申请日：2012-03-30
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L29/78 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/08
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface. An insulated gate electrode is disposed on top of the second surface for controlling a source to drain current and a source electrode is interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region, An epitaxial layer is disposed above and having a different dopant concentration than the drain region. The gate electrode is insulated from the source electrode by an insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种新的开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的半导体的第二表面附近的源极区域。绝缘栅电极设置在第二表面的顶部，用于控制源极到漏极电流，并且源电极插入到绝缘栅电极中，用于基本上防止栅极电极和绝缘栅极之间的外延区域之间的电场的耦合栅电极。源极电极进一步覆盖并延伸在绝缘栅上，用于覆盖半导体的第二表面上的区域以接触源极区。外延层设置在漏极区之上并且具有不同掺杂剂浓度。栅极通过具有取决于垂直功率器件的Vgsmax额定值的厚度的绝缘层与源电极绝缘。

10. 发明授权

US07659570B2 Power MOSFET device structure for high frequency applications 有权
标题翻译：功率MOSFET器件结构用于高频应用
公开(公告)号：US07659570B2
公开(公告)日：2010-02-09
申请号：US11125506
申请日：2005-05-09
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式