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1. 发明授权

US6141285A Power down scheme for regulated sense amplifier power in dram 有权
标题翻译：用于稳压放大器功率的断电方案
公开(公告)号：US6141285A
公开(公告)日：2000-10-31
申请号：US510946
申请日：2000-02-22
申请人： Hon-Shing Lau , Jeng-Feng Lan , Jr-Houng Lu
发明人： Hon-Shing Lau , Jeng-Feng Lan , Jr-Houng Lu
IPC分类号： G11C11/4091 , G11C7/00
CPC分类号： G11C11/4091
摘要： A power down scheme for a regulated sense amplifier power in DRAM. The power-supply level voltage Vccsa of a sense amplifier is turned on only within a certain time duration, which has no relationship with the word line turn-on time. The power down scheme includes control logic gates and time delay circuits which can be triggered by two internal control signals from other control modules in order to generate a power-down control signal for the bit line sense amplifier.
摘要翻译：用于DRAM中调节读出放大器功率的掉电方案。读出放大器的电源电平电压Vccsa仅在一定时间内被接通，这与字线接通时间没有关系。断电方案包括控制逻辑门和时间延迟电路，其可以由来自其他控制模块的两个内部控制信号触发，以产生位线读出放大器的掉电控制信号。

2. 发明授权

US06249473B1 Power down system for regulated internal voltage supply in DRAM 有权
标题翻译：用于DRAM内部稳压内部电源的掉电系统
公开(公告)号：US06249473B1
公开(公告)日：2001-06-19
申请号：US09510436
申请日：2000-02-21
申请人： Hon-Shing Lau , Jeng-Feng Lan , Jr-Houng Lu
发明人： Hon-Shing Lau , Jeng-Feng Lan , Jr-Houng Lu
IPC分类号： G11C700
CPC分类号： G11C11/406 , G11C11/4074
摘要： A power down system for regulated internal power supply in DRAM comprises a RAS control module, self-refresh clock control circuit, and a power down control circuit. The RAS control module responds with row address strobe signals to output a first power down control signal. While all the row address strobe signals, which denote states of the memory banks, are in a first condition of inactivity, the first power down control signal will inform the power down system to turn off a regulator in the DRAM under the first condition. The self-refresh clock control circuit responds with a self-refresh clock to output a second power down control signal. While the self-refresh clock is in a second condition of non-self-refresh mode, the second power down control signal will inform the power down system to turn off the regulator under the second condition. The power down control circuit coupling with the ras control module and self-refresh clock control circuit receives an input clock enable signal, the first power down control signal, and the third power down control signal to output a power down signal to turn off the regulator.
摘要翻译：用于DRAM内部稳压内部电源的掉电系统包括RAS控制模块，自刷新时钟控制电路和掉电控制电路。 RAS控制模块用行地址选通信号进行响应，以输出第一个掉电控制信号。虽然表示存储体的状态的所有行地址选通信号处于不活动的第一状态，但是在第一条件下，第一掉电控制信号将通知断电系统以关闭DRAM中的稳压器。自刷新时钟控制电路以自刷新时钟响应以输出第二掉电控制信号。当自刷新时钟处于非自刷新模式的第二状态时，第二掉电控制信号将通知掉电系统在第二条件下关闭稳压器。与ras控制模块和自刷新时钟控制电路耦合的掉电控制电路接收输入时钟使能信号，第一掉电控制信号和第三掉电控制信号，输出掉电信号以关断稳压器。

3. 发明授权

US6150847A Device and method for generating a variable duty cycle clock 有权
标题翻译：用于产生可变占空比时钟的装置和方法
公开(公告)号：US6150847A
公开(公告)日：2000-11-21
申请号：US358013
申请日：1999-07-21
申请人： Jr-Houng Lu
发明人： Jr-Houng Lu
IPC分类号： G06F1/08 , H03K5/156 , H03K19/00
CPC分类号： G06F1/08 , H03K5/1565
摘要： A device for generating a variable duty cycle clock is provided, which includes a frequency divider, a plurality of first M-stage delay elements, a plurality of second M-stage delay elements, a selector and a logic gate, where M is an integer. The frequency divider divides an input clock to obtain a divided clock. The first M-stage delay elements, which are connected in series, sequentially delay the divided clock for a first delay time to obtain M first delay clocks. The second M-stage delay elements, which are also connected in series and are corresponding to the first M-stage delay elements, sequentially delay the divided clock for a second delay time to obtain M second delay clocks. The second delay time is in a variable proportion to the first delay time. The selector compares the divided clock and each of the M first delay clocks to obtain M state signals. The M state signals are used to select a first selected clock corresponding to a period of the input clock from the first delay clocks, and a second selected clock corresponding to the first selected clock from the second delay clocks. The logic gate XORs the divided clock and the second selected clock to obtain the variable duty cycle clock.
摘要翻译：提供一种用于产生可变占空比时钟的装置，其包括分频器，多个第一M级延迟元件，多个第二M级延迟元件，选择器和逻辑门，其中M是整数。分频器分频输入时钟以获得分频时钟。串联连接的第一M级延迟元件顺序地将分频时钟延迟第一延迟时间以获得M个第一延迟时钟。串联连接并对应于第一M级延迟元件的第二M级延迟元件依次将分频时钟延迟第二延迟时间以获得M秒延迟时钟。第二延迟时间与第一延迟时间成比例变化。选择器比较分频时钟和每个M个第一延迟时钟以获得M个状态信号。 M状态信号用于从第一延迟时钟中选择对应于输入时钟的周期的第一选定时钟，以及从第二延迟时钟对应于第一选定时钟的第二选定时钟。逻辑门将分频时钟和第二选定时钟异或，以获得可变占空比时钟。

4. 发明授权

US06393510B1 Low power high-speed bus receiver 有权
标题翻译：低功率高速总线接收器
公开(公告)号：US06393510B1
公开(公告)日：2002-05-21
申请号：US09400353
申请日：1999-09-20
申请人： Jr-Houng Lu
发明人： Jr-Houng Lu
IPC分类号： G06F1300
CPC分类号： G06F13/4072
摘要： A low power high-speed bus receiver which receives a pair of differential signals to obtain the corresponding logic value is provided. The bus receiver includes a differential amplifier, a pair of input switches and a pair of power switches. The differential amplifier has a pair of input terminals and a pair of power terminals. The pair of input switches are respectively connected between the pair of input terminals of the differential amplifier and the pair of differential signals. The pair of input switches are turned on for a predetermined time period to transmit the pair of differential signals to the differential amplifier. The pair of power switches are respectively connected between the pair of power terminals of the differential amplifier and a pair of external power supplies. The pair of power switches are turned on after the pair of input switches are turned on for the predetermined time period to enable the differential amplifier to amplify the difference between the pair of differential signals to obtain the corresponding logic value.
摘要翻译：提供接收一对差分信号以获得相应逻辑值的低功率高速总线接收器。总线接收器包括差分放大器，一对输入开关和一对电源开关。差分放大器具有一对输入端子和一对电源端子。一对输入开关分别连接在差分放大器的一对输入端和一对差分信号之间。一对输入开关接通预定时间段，以将差分信号对发送到差分放大器。该对电源开关分别连接在差分放大器的一对电源端子和一对外部电源之间。在一对输入开关接通预定时间段之后，一对电源开关导通，使得差分放大器能够放大该对差分信号之间的差异以获得相应的逻辑值。

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