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1. 发明授权

US08896351B2 Line driver method and apparatus 有权
标题翻译：线路驱动方法和装置
公开(公告)号：US08896351B2
公开(公告)日：2014-11-25
申请号：US12051254
申请日：2008-03-19
申请人： Holger Wenske , Thomas Eichler , Mario Traber
发明人： Holger Wenske , Thomas Eichler , Mario Traber
IPC分类号： H03K3/00 , H04L25/02
CPC分类号： H04L25/0264
摘要： According to one embodiment, a line driver circuit comprises a plurality of output stages each operable to produce an output signal and one or more pre-output stages operable to perform one or more common functions. The line driver circuit also comprises circuitry operable to selectively couple one or more of the output stages to the one or more pre-output stages based on a wireline communication technology implemented by the line driver circuit.
摘要翻译：根据一个实施例，线路驱动器电路包括多个输出级，每个输出级可操作以产生输出信号，以及可操作以执行一个或多个共同功能的一个或多个预输出级。线路驱动器电路还包括可操作以基于由线路驱动器电路实现的有线通信技术来将一个或多个输出级选择性地耦合到一个或多个预输出级的电路。

2. 发明申请

US20090237122A1 Line Driver Method and Apparatus 有权
标题翻译：线路驱动器方法和装置
公开(公告)号：US20090237122A1
公开(公告)日：2009-09-24
申请号：US12051254
申请日：2008-03-19
申请人： Holger Wenske , Thomas Eichler , Mario Traber
发明人： Holger Wenske , Thomas Eichler , Mario Traber
IPC分类号： H03K3/00
CPC分类号： H04L25/0264
摘要： According to one embodiment, a line driver circuit comprises a plurality of output stages each operable to produce an output signal and one or more pre-output stages operable to perform one or more common functions. The line driver circuit also comprises circuitry operable to selectively couple one or more of the output stages to the one or more pre-output stages based on a wireline communication technology implemented by the line driver circuit.
摘要翻译：根据一个实施例，线路驱动器电路包括多个输出级，每个输出级可操作以产生输出信号，以及可操作以执行一个或多个共同功能的一个或多个预输出级。线路驱动器电路还包括可操作以基于由线路驱动器电路实现的有线通信技术来将一个或多个输出级选择性地耦合到一个或多个预输出级的电路。

3. 发明申请

US20050195925A1 Process and device for the prediction of noise contained in a received signal 有权
标题翻译：用于预测包含在接收信号中的噪声的过程和装置
公开(公告)号：US20050195925A1
公开(公告)日：2005-09-08
申请号：US10992902
申请日：2004-11-19
申请人： Mario Traber
发明人： Mario Traber
IPC分类号： H04L1/00 , H04L1/20 , H04L27/06
CPC分类号： H04L1/20 , H04L1/0054 , H04L1/006 , H04L2025/03496
摘要： Process and device for the prediction of noise contained in a received signal For predicting noise (n) contained in a received signal (u) transmitted via a transmission channel (2), it is proposed that the autocorrelation function of the received signal (u) is obtained in order to determine noise estimated values for the noise (n) contained in the received signal (u) on the basis of the autocorrelation function. On the basis of the noise-estimated values determined thereby metrics can be updated in a decider in the form of a Viterbi decoder (6), in order to make correct decisions.
摘要翻译：用于预测包含在接收信号中的噪声的处理和装置为了预测通过传输信道（2）发送的接收信号（u）中包含的噪声（n），建议接收信号（u）的自相关函数以便基于自相关函数来确定包含在接收信号（u）中的噪声（n）的噪声估计值。基于由此确定的噪声估计值，可以以维特比解码器（6）的形式在判定器中更新度量，以便做出正确的决定。

4. 发明申请

US20050249320A1 Method and device for digital filtering of interpolated values 有权
标题翻译：用于内插值数字滤波的方法和装置
公开(公告)号：US20050249320A1
公开(公告)日：2005-11-10
申请号：US10650565
申请日：2003-08-27
申请人： Mario Traber
发明人： Mario Traber
IPC分类号： H03H17/02 , H03M7/30 , H03M7/46 , H04L27/26 , H04B1/10
CPC分类号： H03M7/46 , H03H17/02 , H03M7/30 , H04L27/2662
摘要： In the digital filtering of an input signal (3), which has been produced by interpolation of a pilot signal (2), under certain circumstances numerous values originating from the past have to be stored. In order to reduce the storage space required for these and the associated power consumption, the values of the input signal (3), which are needed for computation of the values of an output signal (4), are compressed and stored in compressed form. More particularly here the values of the input signal (3) are divided into symbol periods, in which a coherent range of memory values, which are the only data-carrying values in the symbol period, occurs in each case. These values are stored together with the length of the symbol period, so that although each symbol period can be described completely, storage space is reduced. The values to be stored can be seamlessly stored in a FIFO memory, whereby an address is determined as a function of the length of the symbol periods, under which the desired value can be accessed in the FIFO memory. If the computing specifications of the digital filter require that a non-data carrying value, which is not stored in the FIFO memory has to be accessed, this value is reconstructed, and in particular the data-carrying value immediately preceding in the time sequence and therefore having been input in the FIFO memory, is used.
摘要翻译：在通过导频信号（2）的内插产生的输入信号（3）的数字滤波中，在某些情况下，必须存储来自过去的许多值。为了减少这些所需的存储空间和相关的功耗，计算输出信号（4）的值所需的输入信号（3）的值被压缩并以压缩形式存储。更具体地，输入信号（3）的值被划分为符号周期，其中在每种情况下都发生作为符号周期中唯一的数据携带值的存储器值的相干范围。这些值与符号周期的长度一起存储，使得尽管可以完全描述每个符号周期，但是减少了存储空间。要存储的值可以无缝地存储在FIFO存储器中，由此根据符号周期的长度确定地址，在FIFO存储器中可以访问期望值。如果数字滤波器的计算规范要求必须访问不存储在FIFO存储器中的非数据携带值，则重建该值，特别是在时间序列中紧接在前的数据携带值，以及因此已被输入到FIFO存储器中。

5. 发明申请

US20070220073A1 Digital filter and method for designing digital filters 审中-公开
标题翻译：数字滤波器和数字滤波器设计方法
公开(公告)号：US20070220073A1
公开(公告)日：2007-09-20
申请号：US11545838
申请日：2006-10-11
申请人： Mario Traber
发明人： Mario Traber
IPC分类号： G06F15/00
CPC分类号： H03H17/0288 , H03H17/0277 , H03H17/0416 , H03H17/0444 , H03H17/045
摘要： A digital filter comprises a plurality of filter units each realizing mutually independent filter functions with a predetermined recursive filter order on a signal path between the input and the output of the filter and operating at a first clock rate, a plurality of sampling devices operating at the first clock rate, and a weighting network coupled to the sampling devices and operating at a second clock rate. The filter units comprise at least one delay element which can be reset to a predeterminable value. To each of the filter units one of the sampling devices is allocated setting the respective delay element to a predetermined value dependent on a sampling rate conversion factor. An input signal is conducted, via the weighting network, to a respective sampling device, or digital internal sampling signals output by a respective sampling device are conducted to the output via the weighting network.
摘要翻译：数字滤波器包括多个滤波器单元，每个滤波器单元在滤波器的输入和输出之间的信号路径上以预定的递归滤波器顺序实现相互独立的滤波器功能，并以第一时钟速率工作;多个采样装置第一时钟速率和耦合到采样设备并以第二时钟速率操作的加权网络。滤波器单元包括至少一个可被重置为可预定值的延迟元件。对于每个滤波器单元，分配采样设备之一，根据采样率转换因子将相应的延迟元件设置为预定值。通过加权网络将输入信号传送到相应的采样装置，或者由相应采样装置输出的数字内部采样信号通过加权网络被传送到输出端。

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