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1. 发明授权

US06954387B2 Dynamic random access memory with smart refresh scheduler 有权
标题翻译：具有智能刷新调度器的动态随机存取存储器
公开(公告)号：US06954387B2
公开(公告)日：2005-10-11
申请号：US10604375
申请日：2003-07-15
申请人： Hoki Kim , Toshiaki Kirihata , David R. Hanson , Gregory J. Fredeman , John Golz
发明人： Hoki Kim , Toshiaki Kirihata , David R. Hanson , Gregory J. Fredeman , John Golz
IPC分类号： G11C11/406 , G11C7/00 , G11C8/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C2207/104
摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.
摘要翻译：在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。每个组的比较器提供一个比较器输出。每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。仲裁器被连接以接收信号中的冲突并提供冲突信号。一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。

2. 发明授权

US06768143B1 Structure and method of making three finger folded field effect transistors having shared junctions 失效
标题翻译：制造具有共同连接点的三指折叠场效应晶体管的结构和方法
公开(公告)号：US06768143B1
公开(公告)日：2004-07-27
申请号：US10604913
申请日：2003-08-26
申请人： Gregory J. Fredeman , John W. Golz , David R. Hanson , Hoki Kim
发明人： Gregory J. Fredeman , John W. Golz , David R. Hanson , Hoki Kim
IPC分类号： H01L2710
CPC分类号： H01L27/10897 , G11C11/4085
摘要： An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.
摘要翻译：提供了包括场效应晶体管（FET）的集成电路，其中栅极导通器具有设置在衬底的交替的源极和漏极区域之间的偶数个指状物。手指在图案上设置有在水平方向上具有长度的区域的区域，该区域等于长度乘以由奇数手指占据的垂直方向上的宽度。

3. 发明授权

US07404113B2 Flexible row redundancy system 有权
标题翻译：灵活的行冗余系统
公开(公告)号：US07404113B2
公开(公告)日：2008-07-22
申请号：US11031138
申请日：2005-01-07
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 复制逻辑模块被编程为根据可选择的修复字段大小将至少一个故障地址复制到存储在对应于预定数量的存储体的行熔丝阵列中的行熔丝信息中。

4. 发明授权

US07085180B2 Method and structure for enabling a redundancy allocation during a multi-bank operation 失效
标题翻译：在多行操作期间实现冗余分配的方法和结构
公开(公告)号：US07085180B2
公开(公告)日：2006-08-01
申请号：US10777596
申请日：2004-02-12
申请人： Gregory J. Fredeman , Mark D. Jacunski , Toshiaki Kirihata , Matthew R. Wordeman
发明人： Gregory J. Fredeman , Mark D. Jacunski , Toshiaki Kirihata , Matthew R. Wordeman
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/4401 , G11C29/40 , G11C29/44 , G11C29/808 , G11C2029/0401 , G11C2029/2602
摘要： A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.
摘要翻译：描述了在包括两个或更多个冗余域的存储器设备中在多存储体操作期间分配冗余的方法。该方法包括启用通过/故障位检测来激活给定的存储体的步骤。通过/失败位检测仅对选定的域提示，并且在寻址其他域时被禁用。通过改变域选择，无论多行操作如何，都可以为任何域启用冗余分配。该方法可以优选地通过使用具有真实和补充预期数据对的动态异或逻辑来实现。当结合简单的指针逻辑时，可以内部生成域的选择，简化内置的自检和其他测试控制协议，同时跟踪失败的那些。

5. 发明授权

US07774660B2 Flexible row redundancy system 失效
标题翻译：灵活的行冗余系统
公开(公告)号：US07774660B2
公开(公告)日：2010-08-10
申请号：US12131307
申请日：2008-06-02
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

6. 发明授权

US07194670B2 Command multiplier for built-in-self-test 有权
标题翻译：内置自检命令乘数
公开(公告)号：US07194670B2
公开(公告)日：2007-03-20
申请号：US10708184
申请日：2004-02-13
申请人： Jonathan R. Fales , Gregory J. Fredeman , Kevin W. Gorman , Mark D. Jacunski , Toshiaki Kirihata , Alan D. Norris , Paul C. Parries , Matthew R. Wordeman
发明人： Jonathan R. Fales , Gregory J. Fredeman , Kevin W. Gorman , Mark D. Jacunski , Toshiaki Kirihata , Alan D. Norris , Paul C. Parries , Matthew R. Wordeman
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/12015 , G11C29/14 , G11C2029/0401
摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.
摘要翻译：公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。

7. 发明授权

US07817455B2 Random access electrically programmable e-fuse ROM 有权
标题翻译：随机存取电可编程电子熔丝ROM
公开(公告)号：US07817455B2
公开(公告)日：2010-10-19
申请号：US12065202
申请日：2006-08-30
申请人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027
摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp, for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.
摘要翻译：一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。通过在VDD处工作的解码逻辑执行字线选择，同时位线驱动器在VDD和较高电压Vp之间切换，用于编程。因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

8. 发明申请

US20080316789A1 Random Access Electrically Programmable E-Fuse Rom 有权
标题翻译：随机存取电子可编程电子保险丝
公开(公告)号：US20080316789A1
公开(公告)日：2008-12-25
申请号：US12065202
申请日：2006-08-30
申请人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C17/00 , G11C17/16
CPC分类号： G11C17/16 , G11C17/165 , G11C29/027
摘要： A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at VDD while the bit line drive is switched between VDD and a higher voltage, Vp for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.
摘要翻译：一次性可编程只读存储器（OTPROM）在二维阵列中实现，这些阵列具有大规模的自杀可迁移电子保险丝。字线选择通过在VDD处工作的解码逻辑进行，而位线驱动器在VDD和较高电压Vp之间切换，用于编程。因此，OTPROM与其他技术兼容，并且可以与其他技术集成，而无需使用成本加法器，并支持在熔丝编程期间最小化电压降的高电流路径的优化。具有可编程参考的差分读出放大器用于改进的检测余量，并且可以支持整个位线，而不是为各个保险丝提供感测放大器。

9. 发明申请

US20080229144A1 FLEXIBLE ROW REDUNDANCY SYSTEM 失效
标题翻译：灵活的冗余系统
公开(公告)号：US20080229144A1
公开(公告)日：2008-09-18
申请号：US12131307
申请日：2008-06-02
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G06F11/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

10. 发明授权

US07609577B2 Design structure for improving sensing margin of electrically programmable fuses 有权
标题翻译：用于提高电可编程保险丝感应裕度的设计结构
公开(公告)号：US07609577B2
公开(公告)日：2009-10-27
申请号：US11872273
申请日：2007-10-15
申请人： Darren L. Anand , Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
发明人： Darren L. Anand , Gregory J. Fredeman , Toshiaki Kirihata , Alan J. Leslie , John M. Safran
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C17/165 , G11C17/18 , G11C29/027
摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构包括用于感测可编程电阻性存储元件装置的状态的装置，该装置还包括耦合到熔丝节点和参考节点的锁存装置，所述熔丝节点包括所述锁存装置被配置为检测在所述参考节点和所述熔丝节点之间产生的差动信号，这是由于感测电流通过所述保险丝腿和所述参考电阻腿的结果; 并且熔丝和参考电阻腿进一步配置用于第一和第二感测模式，其中第二感测模式利用与第一感测模式不同的电流电平。

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