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1. 发明申请

US20050013185A1 DYNAMIC RANDOM ACCESS MEMORY WITH SMART REFRESH SCHEDULER 有权
标题翻译：动态随机存取存储器与SMART REFRESH SCHEDULER
公开(公告)号：US20050013185A1
公开(公告)日：2005-01-20
申请号：US10604375
申请日：2003-07-15
申请人： Hoki Kim , Toshiaki Kirihata , David Hanson , Gregory Fredeman , John Golz
发明人： Hoki Kim , Toshiaki Kirihata , David Hanson , Gregory Fredeman , John Golz
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C2207/104
摘要： In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.
摘要翻译：在包括多个存储体的DRAM中，对于每个存储体，存在分别向上/向下移位的标志位寄存器的一对分离的标志位寄存器。每个组的比较器提供一个比较器输出。每个存储体的仲裁器被连接以从该存储体的标志位寄存器和对于该存储体的比较器输出的比较器输出标志位向上信号和标志位降低信号。仲裁器被连接以接收信号中的冲突并提供冲突信号。一对标志位寄存器表示每个存储体的刷新状态，并指定准备进行刷新操作的存储体或阵列。

2. 发明申请

US20060039226A1 LOW POWER MANAGER FOR STANDBY OPERATION OF A MEMORY SYSTEM 有权
标题翻译：低功耗管理器，用于存储系统的待机操作
公开(公告)号：US20060039226A1
公开(公告)日：2006-02-23
申请号：US11205565
申请日：2005-08-17
申请人： David Hanson , Gregory Fredeman , John Golz , Hoki Kim , Paul Parries
发明人： David Hanson , Gregory Fredeman , John Golz , Hoki Kim , Paul Parries
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C8/08
摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
摘要翻译：存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线司机。具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

3. 发明申请

US20060273841A1 PROGRAMMING AND DETERMINING STATE OF ELECTRICAL FUSE USING FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES 失效
标题翻译：使用具有多个导通状态的场效应晶体管编程和确定电子熔丝状态
公开(公告)号：US20060273841A1
公开(公告)日：2006-12-07
申请号：US11160056
申请日：2005-06-07
申请人： David Hanson , Dureseti Chidambarrao , Gregory Fredeman , David Onsongo
发明人： David Hanson , Dureseti Chidambarrao , Gregory Fredeman , David Onsongo
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A circuit is provided which is operable to program an electrically alterable element, e.g., fuse or antifuse, to a programmed state and determine whether the electrically alterable element is in the programmed state or not. Such circuit includes a multiple conduction state field effect transistor (“multi-state FET”) having at least one of a source or a drain coupled to the electrically alterable element to apply a current to the electrically alterable element. The multi-state FET has a first threshold voltage and a second threshold voltage, both being effective at the same time, the second threshold voltage being higher than the first threshold voltage. The gate is operable to control operation of the multi-state FET in multiple states including a) an essentially nonconductive state; b) a first or “low” conductive state when a gate-source voltage exceeds the first threshold voltage, in which the multi-state FET is biased to conduct a relatively low magnitude current for determining the state of the fuse; and c) a second conductive state when the gate-source voltage exceeds the second threshold voltage, in which the multi-state FET is biased to conduct a relatively high magnitude programming current.
摘要翻译：提供了一种电路，其可操作以将电可更改元件（例如，熔丝或反熔丝）编程到编程状态，并确定电可更改元件是否处于编程状态。这种电路包括多导通状态场效应晶体管（“多状态FET”），其具有耦合到可电可变元件的源极或漏极中的至少一个，以将电流施加到电可更改元件。多状态FET具有第一阈值电压和第二阈值电压，两者均同时有效，第二阈值电压高于第一阈值电压。栅极可操作以控制多状态FET的操作，包括a）基本上非导通状态; b）当栅极 - 源极电压超过第一阈值电压时，第一或“低”导通状态，其中多态FET被偏置以传导相对低的幅度电流以确定保险丝的状态; 以及c）当所述栅极 - 源极电压超过所述第二阈值电压时，所述第二导电状态是所述多态FET被偏置以导通相对高的编程电流。

4. 发明授权

US6081479A Hierarchical prefetch for semiconductor memories 有权
标题翻译：半导体存储器的分层预取
公开(公告)号：US6081479A
公开(公告)日：2000-06-27
申请号：US333539
申请日：1999-06-15
申请人： Brian Ji , Toshiaki Kirihata , Gerhard Mueller , David Hanson
发明人： Brian Ji , Toshiaki Kirihata , Gerhard Mueller , David Hanson
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1039
摘要： A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.
摘要翻译：根据本发明的半导体存储器包括包括多个分层级的数据路径，每个级包括与其他级不同的位数据速率。至少两个预取电路设置在各级之间。至少两个预取电路包括用于接收数据位并存储数据位的至少两个锁存器，直到层级中的下一级能够接收数据位。所述至少两个预取电路耦合在级之间，使得级之间每级的总体数据速率基本相等。控制信号控制至少两个锁存器，使得预取电路保持级之间的总体数据速率。

5. 发明授权

US06683486B2 Low voltage shifter with latching function 失效
标题翻译：具有锁定功能的低电压转换器
公开(公告)号：US06683486B2
公开(公告)日：2004-01-27
申请号：US10114221
申请日：2002-04-02
申请人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
发明人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
IPC分类号： H03L500
CPC分类号： H03K3/356147 , H03K3/012
摘要： A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.
摘要翻译：具有嵌入式锁存器的低电压电平移位器电路，其在具有低电压信号的信号线上实现。包括低电压电平移位器电路，其配置为从信号线的第一部分接收低电压输入信号，并在信号线的第二部分上输出更高电压的输出信号。还包括锁存电路，并且被配置为锁存来自信号线的第一部分的低电压输入信号。

6. 发明授权

US06370055B1 Semiconductor memory having asymmetric column addressing and twisted read write drive (RWD) line architecture 失效
标题翻译：具有非对称列寻址和双绞读写驱动（RWD）线架构的半导体存储器
公开(公告)号：US06370055B1
公开(公告)日：2002-04-09
申请号：US09795761
申请日：2001-02-28
申请人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
发明人： David Hanson , Gerhard Mueller , Toshiaki Kirihata
IPC分类号： G11C506
CPC分类号： G11C5/063
摘要： There is provided a semiconductor memory having a plurality of memory units. The memory includes a plurality of read write drive (RWD) lines horizontally and/or vertically twisted such that the RWD lines are shared between the plurality of memory units. A plurality of columns is included in each of the plurality of memory units. Each of the plurality of columns is adapted to access the plurality of RWD lines through asymmetrical addressing.
摘要翻译：提供了具有多个存储单元的半导体存储器。存储器包括水平和/或垂直扭转的多个读写驱动（RWD）线，使得RWD线在多个存储器单元之间共享。在多个存储单元的每一个中包括多个列。多个列中的每一个适于通过非对称寻址来访问多个RWD线。

7. 发明申请

US20190171310A1 HUMAN-COMPUTER INTERFACE DEVICE AND SYSTEM 审中-公开
公开(公告)号：US20190171310A1
公开(公告)日：2019-06-06
申请号：US16240822
申请日：2019-01-07
申请人： David Hanson , Spring Power Holdings Limited
发明人： David Hanson
IPC分类号： G06F3/041 , A63F13/20 , G06F3/0354 , A63F13/213 , G06T13/40 , G06T13/00 , G06F3/0488 , G06F3/039 , A63F13/426 , A63F13/424 , A63F13/245 , A63F13/2145
CPC分类号： G06F3/041 , A63F13/20 , A63F13/213 , A63F13/2145 , A63F13/245 , A63F13/424 , A63F13/426 , G06F3/03543 , G06F3/03545 , G06F3/039 , G06F3/0488 , G06F3/04883 , G06F2203/04805 , G06F2203/04809 , G06T13/00 , G06T13/40
摘要： An interface device for a computerized system, the interface device including an engagement element configured for operable engagement with a region on a touchscreen of the computerized system to enable interfacing with the computerized system via the touchscreen, wherein the engagement element includes a viewing surface configured to allow a representation of content that is displayed at the region on the touchscreen with which the engagement element is operably engaged, to be visible through the viewing surface.

8. 发明授权

US09796095B1 System and method for controlling intelligent animated characters 有权
公开(公告)号：US09796095B1
公开(公告)日：2017-10-24
申请号：US13968241
申请日：2013-08-15
申请人： David Hanson , Robert Hauser
发明人： David Hanson , Robert Hauser
IPC分类号： G06F19/00 , G05B19/04 , B25J11/00
CPC分类号： B25J11/0005 , B25J11/001
摘要： A system and method for controlling animated characters. The system involves an animated character mapping perception into a number of domains, including a world domain, linguistic domain and social domain. The system is computationally perceived items that should be abstracted from the character's environment for processing. The animated character is able to utilize different levels of information gathering or learning, different levels of decision making, and different levels of dynamic responses to provide life-like interactions.

9. 发明申请

US20170298339A1 Engineered Stable Microorganism/Cell Communities 审中-公开
公开(公告)号：US20170298339A1
公开(公告)日：2017-10-19
申请号：US15481600
申请日：2017-04-07
申请人： David Hanson , Linnea K. Ista , Plamen B. Atanassov , John Michael Roesgen , Jose Cornejo
发明人： David Hanson , Linnea K. Ista , Plamen B. Atanassov , John Michael Roesgen , Jose Cornejo
IPC分类号： C12N11/04 , C12N1/20 , C02F3/32 , C02F3/00 , C02F3/34 , H01M8/16 , C12N1/12
CPC分类号： C12N11/04 , C02F3/005 , C02F3/322 , C02F3/325 , C02F3/341 , C02F3/345 , C02F3/348 , C02F2303/10 , C12N1/12 , C12N1/20 , H01M4/90 , H01M8/16 , Y02E60/527 , Y02W10/30
摘要： Engineered stable multi-organism (or multi-cell type) communities encapsulated in a media that slows or prohibits certain metabolic functions such as cell division, but maintains other metabolic functions.

10. 发明申请

US20060293032A1 Email SMS notification system providing enhanced message retrieval features and related methods 有权
标题翻译：电子邮件短信通知系统，提供增强的消息检索功能和相关方法
公开(公告)号：US20060293032A1
公开(公告)日：2006-12-28
申请号：US11165309
申请日：2005-06-23
申请人： David Clarke , Harshad Kamat , David Hanson
发明人： David Clarke , Harshad Kamat , David Hanson
IPC分类号： H04Q7/22
CPC分类号： H04L51/24 , H04L51/38 , H04W4/12 , H04W4/14 , H04W88/06 , H04W88/184 , H04W92/02
摘要： A communications system may include at least one wireless communications device and at least one electronic mail (email) server for storing email messages for the at least one wireless communications device. The system may further include an email relay server for detecting a new email message on the at least one email server and, based thereon, sending a short message service (SMS) notification with a unique message identifier (ID) of the new email message to the at least one wireless communications device. Moreover, the at least one wireless communications device may detect the SMS notification and send an email retrieval request to the email relay server instructing the email relay server to retrieve the new email message based upon the unique message ID.
摘要翻译：通信系统可以包括至少一个无线通信设备和用于存储用于至少一个无线通信设备的电子邮件消息的至少一个电子邮件（电子邮件）服务器。系统还可以包括用于在至少一个电子邮件服务器上检测新的电子邮件消息的电子邮件中继服务器，并且基于此，发送具有新电子邮件消息的唯一消息标识符（ID）的短消息服务（SMS）通知，所述至少一个无线通信设备。此外，所述至少一个无线通信设备可以检测SMS通知，并且向电子邮件中继服务器发送电子邮件检索请求，其指示电子邮件中继服务器基于唯一的消息ID来检索新的电子邮件消息。

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