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1. 发明授权

US08023337B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08023337B2
公开(公告)日：2011-09-20
申请号：US12591176
申请日：2009-11-12
申请人： Hoe-Ju Chung , Ki-Whan Song
发明人： Hoe-Ju Chung , Ki-Whan Song
IPC分类号： G11C16/04
CPC分类号： G11C7/06 , G11C7/1012 , G11C7/12 , G11C7/18 , G11C2207/005
摘要： A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding to the number of bit lines, the bit-line selector selects a plurality of bit lines in response to the bit-line indication signal. Thus, it is possible to reduce the number of signals output from the column decoder.
摘要翻译：提供了具有共享读出放大器的半导体存储器件。半导体存储器件具有比列解码器更靠近存储单元阵列设置的位线选择器。当列解码器输出与位线数相对应的位线指示信号时，位线选择器响应于位线指示信号选择多个位线。因此，可以减少从列解码器输出的信号的数量。

2. 发明申请

US20100118616A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20100118616A1
公开(公告)日：2010-05-13
申请号：US12591176
申请日：2009-11-12
申请人： Hoe-Ju Chung , Ki-Whan Song
发明人： Hoe-Ju Chung , Ki-Whan Song
IPC分类号： G11C7/10 , G11C7/00 , G11C8/10
CPC分类号： G11C7/06 , G11C7/1012 , G11C7/12 , G11C7/18 , G11C2207/005
摘要： A semiconductor memory device having shared sense amplifiers is provided. The semiconductor memory device has a bit-line selector disposed closer to a memory cell array than a column decoder. When the column decoder outputs a bit-line indication signal corresponding to the number of bit lines, the bit-line selector selects a plurality of bit lines in response to the bit-line indication signal. Thus, it is possible to reduce the number of signals output from the column decoder.
摘要翻译：提供了具有共享读出放大器的半导体存储器件。半导体存储器件具有比列解码器更靠近存储单元阵列设置的位线选择器。当列解码器输出与位线数相对应的位线指示信号时，位线选择器响应于位线指示信号选择多个位线。因此，可以减少从列解码器输出的信号的数量。

3. 发明申请

US20120300528A1 Stacked Memory Module and System 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US20120300528A1
公开(公告)日：2012-11-29
申请号：US13535363
申请日：2012-06-28
申请人： Uk-song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

4. 发明授权

US08230140B2 Latency control circuit and method using queuing design method 失效
标题翻译：延迟控制电路和使用排队设计方法的方法
公开(公告)号：US08230140B2
公开(公告)日：2012-07-24
申请号：US13178846
申请日：2011-07-08
申请人： Byung-Hoon Jeong , Hoe-Ju Chung
发明人： Byung-Hoon Jeong , Hoe-Ju Chung
IPC分类号： G06F3/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1078 , G11C7/109 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C2207/2272
摘要： A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.
摘要翻译：等待时间控制电路包括FIFO控制器和寄存器单元。 FIFO控制器可以根据外部命令生成增加信号，并根据内部命令生成减少信号。 FIFO控制器还可以响应于增加信号和减小信号启用深度点信号。寄存器单元可以包括n个寄存器。值n（四舍五入）可以通过将最大数量的加性延迟和最大写入延迟数的较大值除以列周期延迟时间（tCCD）来获得。寄存器可以响应于增加信号和时钟信号而存储与外部命令接收的地址，并且可以将地址或先前地址移位到相邻寄存器。延迟控制电路将存储在寄存器中的地址作为与启用的深度点信号相对应的列地址。

5. 发明授权

US08112680B2 System and device with error detection/correction process and method outputting data 有权
标题翻译：具有错误检测/校正处理和方法输出数据的系统和设备
公开(公告)号：US08112680B2
公开(公告)日：2012-02-07
申请号：US12044183
申请日：2008-03-07
申请人： Hoe-Ju Chung , Jung-Bae Lee
发明人： Hoe-Ju Chung , Jung-Bae Lee
IPC分类号： G06F11/00
CPC分类号： G06F11/1008 , G11C5/02 , G11C5/04 , G11C7/02 , G11C7/1006 , G11C7/1045 , G11C2029/0411 , H04L1/0041 , H04L1/0057
摘要： A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.
摘要翻译：系统，设备和相关方法用于经由包括所选择的数据通道的多个数据通道来传送数据。在第一操作模式中，经由包括所选择的数据通道的多个数据通道来传送有效载荷数据和相关的补充数据。在第二种操作模式中，只有有效载荷数据经由多个数据通道被传送，除了所选择的数据通道。

6. 发明授权

US08031505B2 Stacked memory module and system 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US08031505B2
公开(公告)日：2011-10-04
申请号：US12454064
申请日：2009-05-12
申请人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

7. 发明申请

US20090085599A1 Semiconductor device having ESD protection circuit and method of testing the same 有权
标题翻译：具有ESD保护电路的半导体器件及其测试方法
公开(公告)号：US20090085599A1
公开(公告)日：2009-04-02
申请号：US12232592
申请日：2008-09-19
申请人： Young-Don Choi , Hoe-Ju Chung
发明人： Young-Don Choi , Hoe-Ju Chung
IPC分类号： G01R31/26 , H01L23/60
CPC分类号： G01R31/2884 , H01L23/60 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an electrostatic discharge (ESD) protection circuit and a method of testing the same may provided. The semiconductor device may include one or more stacked chips, each stacked chip may include a test circuit configured to output a test control signal and a selection control signal in response to a test enable signal, an internal circuit configured to perform an operation and output a plurality of test signals in response to the test control signal, at least one multiplexer (MUX) configured to select and output one of the plurality of test signals based on the selection control signal, at least one test pad configured to receive the selected test signal, and at least one electrostatic discharge (ESD) protection circuit configured to discharge static electricity applied through the test pad externally.
摘要翻译：可以提供具有静电放电（ESD）保护电路的半导体器件及其测试方法。半导体器件可以包括一个或多个堆叠的芯片，每个堆叠的芯片可以包括测试电路，其被配置为响应于测试使能信号输出测试控制信号和选择控制信号，内部电路被配置为执行操作并输出响应于测试控制信号的多个测试信号，至少一个多路复用器（MUX），被配置为基于选择控制信号选择并输出多个测试信号中的一个;至少一个测试板，被配置为接收所选择的测试信号以及至少一个静电放电（ESD）保护电路，其被配置为从外部排出通过测试焊盘施加的静电。

8. 发明授权

US07447862B2 Memory system and timing control method of the same 有权
标题翻译：存储系统和时序控制方法相同
公开(公告)号：US07447862B2
公开(公告)日：2008-11-04
申请号：US10886926
申请日：2004-07-08
申请人： Jung-Bae Lee , Hoe-Ju Chung
发明人： Jung-Bae Lee , Hoe-Ju Chung
IPC分类号： G06F13/42
CPC分类号： G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C2207/2254
摘要： A memory system includes at least one memory module, each of which has a pattern data generating circuit for generating a pattern data, which has a plurality of memories to which a command signal is commonly applied and corresponding data is applied respectively; and a memory controller for respectively applying the command signal and the corresponding data to the plurality of memories, applying a pattern data generating command to the memory module during a timing control operation, calculating time differences among data of reaching each of the plurality of memories using the pattern data outputted from each of the memories and receiving and outputting data using the calculated data reaching time difference. Therefore, a stable data transmission is achieved between the memory controller and the memories.
摘要翻译：存储器系统包括至少一个存储器模块，每个存储器模块具有用于产生模式数据的模式数据产生电路，该模式数据具有共同应用命令信号的多个存储器，并且分别应用相应的数据; 以及存储器控制器，用于分别将命令信号和相应的数据应用于多个存储器，在定时控制操作期间向存储器模块应用模式数据产生命令，使用以下方式计算到达多个存储器中的每一个的数据之间的时间差：从每个存储器输出的图案数据，并使用计算出的数据到达时间差来接收和输出数据。因此，在存储器控制器和存储器之间实现稳定的数据传输。

9. 发明授权

US07426149B2 Semiconductor memory module and semiconductor memory device 有权
标题翻译：半导体存储器模块和半导体存储器件
公开(公告)号：US07426149B2
公开(公告)日：2008-09-16
申请号：US11540607
申请日：2006-10-02
申请人： Seok-Il Kim , You-Keun Han , Hoe-Ju Chung , Young-Man Ahn
发明人： Seok-Il Kim , You-Keun Han , Hoe-Ju Chung , Young-Man Ahn
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C5/04 , G11C29/025 , H05K1/0268 , H05K1/181
摘要： A semiconductor memory module and a semiconductor memory device are disclosed. In one embodiment, the invention provides a semiconductor memory module comprising a circuit board, a plurality of semiconductor memory devices adapted to operate during a test mode and a normal operation mode and mounted on the circuit board, a first signal line set comprising a plurality of first signal lines connected to the plurality of semiconductor memory devices, and a plurality of second signal line sets. Each semiconductor memory device comprises first terminals adapted to receive first signals from the first signal lines, second terminals connected to a corresponding one of the second signal line sets, a third terminal adapted to receive an enable signal during the test mode, and a signal transmitting unit adapted to output second signals to the second terminals in response to the enable signal.
摘要翻译：公开了半导体存储器模块和半导体存储器件。在一个实施例中，本发明提供了一种半导体存储器模块，包括电路板，多个半导体存储器件，适于在测试模式和正常操作模式下操作并安装在电路板上，第一信号线组包括多个连接到多个半导体存储器件的第一信号线，以及多个第二信号线组。每个半导体存储器件包括适于从第一信号线接收第一信号的第一端子，连接到第二信号线组中对应的一个信号线组的第二端子，适于在测试模式期间接收使能信号的第三端子，以及信号发送该单元适于响应于使能信号将第二信号输出到第二终端。

10. 发明申请

US20070271424A1 Memory module, a memory system including a memory controller and a memory module and methods thereof 失效
标题翻译：存储器模块，包括存储器控制器和存储器模块的存储器系统及其方法
公开(公告)号：US20070271424A1
公开(公告)日：2007-11-22
申请号：US11723821
申请日：2007-03-22
申请人： Jung-Bae Lee , Hoe-Ju Chung
发明人： Jung-Bae Lee , Hoe-Ju Chung
IPC分类号： G06F12/00
CPC分类号： G06F13/1668
摘要： A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface and at least one memory device. An example write operation method may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal, an address and write data from the received packet command if the received packet command corresponds to a write operation, transferring the extracted write data to at least one memory device via write/read data lines internal to the given one memory unit and writing the transferred write data at the at least one memory device. An example read operation may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal and an address from the received packet command if the received packet command corresponds to a read operation, transferring the extracted command signal and address to at least one memory device, receiving read data corresponding to the extracted command signal and address from the at least one memory device via write/read data lines internal to the given one memory unit and transmitting the received read data from the interface via read data lines external to the given one memory unit.
摘要翻译：存储器模块，包括存储器控制器和存储器模块的存储器系统及其方法。示例性存储器模块可以包括多个存储单元，每个存储器单元具有接口和至少一个存储器件。示例性写入操作方法可以包括在多个存储器单元中的给定一个处接收分组命令，所述多个存储器单元中的每一个包括接口和至少一个存储器设备，提取命令信号，地址和写入数据如果接收到的分组命令对应于写入操作，则接收到的分组命令，通过给定一个存储器单元内部的写入/读取数据线将提取的写入数据传送到至少一个存储器件，并将传送的写入数据写入至少一个存储设备。示例性读取操作可以包括在多个存储器单元中的给定一个处接收分组命令，所述多个存储器单元中的每一个包括接口和至少一个存储器设备，从接收到的分组命令中提取命令信号和地址如果接收的分组命令对应于读取操作，则将所提取的命令信号和地址传送到至少一个存储器件，通过内部的写入/读取数据线从至少一个存储器件接收与所提取的命令信号和地址相对应的读取数据到给定的一个存储器单元，并且通过给定的一个存储器单元外部的读取数据线从接口发送接收到的读取数据。

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