专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080283994A1 Stacked package structure and fabrication method thereof 审中-公开
标题翻译：堆叠封装结构及其制造方法
公开(公告)号：US20080283994A1
公开(公告)日：2008-11-20
申请号：US12152687
申请日：2008-05-16
申请人： Ho-Yi Tsai , Chien-Ping Huang , Jung-Pin Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
发明人： Ho-Yi Tsai , Chien-Ping Huang , Jung-Pin Huang , Chin-Huang Chang , Cheng-Hsu Hsiao
IPC分类号： H01L23/49 , H01L21/56
CPC分类号： H01L23/49816 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/1134 , H01L2224/1308 , H01L2224/1411 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H05K3/3436 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked package structure and fabrication method thereof are disclosed, including providing a substrate having a plurality of stackable solder pads formed on surface thereof for allowing at least one semiconductor chip to be electrically connected to the substrate; forming an encapsulant for encapsulating the semiconductor chip and further exposing the stackable solder pads from the encapsulant, thus forming a lower-layer semiconductor package; forming conductive bumps on at least one stackable solder pad by means of wire bonding such that at least one upper-layer semiconductor package can be mounted via solder balls on the conductive bumps and the stackable solder pads of the lower-layer semiconductor package to form a stacked package structure, wherein, stacking height of the solder balls and the conductive bumps is greater than height of the encapsulant of the lower-layer semiconductor package, thus, when stacking fine pitch semiconductor packages or when warps occur to the upper-layer semiconductor package or the lower-layer semiconductor package, the conductive bumps can compensate for inadequate height caused by solder ball collapse or fill up gaps between the solder balls and the stackable solder pads caused by warps, thereby allowing the solder balls to be able to effectively contact and wet on the substrate of the lower-layer semiconductor package.
摘要翻译：公开了一种堆叠封装结构及其制造方法，包括提供一种具有形成在其表面上的多个可叠置焊料焊盘的衬底，用于允许至少一个半导体芯片电连接到衬底; 形成用于封装半导体芯片的密封剂，并进一步从可密封剂暴露可堆叠的焊盘，从而形成下层半导体封装; 通过引线接合在至少一个可堆叠的焊盘上形成导电凸块，使得至少一个上层半导体封装可以经由焊球安装在导电凸块和下层半导体封装的可堆叠焊盘上，以形成堆叠的封装结构，其中，焊球和导电凸块的堆叠高度大于下层半导体封装的密封剂的高度，因此，当堆叠精细间距半导体封装时或当上行半导体封装发生翘曲时或下层半导体封装，导电凸块可以补偿由焊球塌陷引起的不适当的高度，或填充由经线引起的焊球和可堆叠焊盘之间的间隙，从而允许焊球能够有效地接触和在下层半导体封装的衬底上湿润。

2. 发明申请

US20100255635A1 FABRICATION METHOD OF MULTI-CHIP STACK STRUCTURE 有权
标题翻译：多芯片堆叠结构的制作方法
公开(公告)号：US20100255635A1
公开(公告)日：2010-10-07
申请号：US12818701
申请日：2010-06-18
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L21/60
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

3. 发明申请

US20080224289A1 Multi-chip stack structure and fabrication method thereof 有权
标题翻译：多芯片堆叠结构及其制造方法
公开(公告)号：US20080224289A1
公开(公告)日：2008-09-18
申请号：US12077003
申请日：2008-03-13
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

4. 发明授权

US07981729B2 Fabrication method of multi-chip stack structure 有权
标题翻译：多芯片堆叠结构的制作方法
公开(公告)号：US07981729B2
公开(公告)日：2011-07-19
申请号：US12818701
申请日：2010-06-18
申请人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
发明人： Jung-Pin Huang , Chin-Huang Chang , Chien-Ping Huang , Chung-Lun Liu , Cheng-Hsu Hsiao
IPC分类号： H01L21/60
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/50 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48496 , H01L2224/49175 , H01L2224/78 , H01L2224/85001 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00
摘要： A multi-chip stack structure and a fabrication method thereof are proposed, including providing a leadframe having a die base and a plurality of leads and disposing a first and a second chips on the two surfaces of the die base respectively; disposing the leadframe on a heating block having a cavity in a wire bonding process with the second chip received in the cavity of the heating block; performing a first wire bonding process to electrically connect the first chip to the leads through a plurality of first bonding wires, and forming a bump on one side of the leads connected with the first bonding wires; disposing the leadframe in an upside down manner to the heating block via the bump with the first chip and the first bonding wires received in the cavity of the heating block; and performing a second wire bonding process to electrically connect the second chip to the leads through a plurality of second bonding wires. The bump is used for supporting the leads to a certain height so as to keep the bonding wires from contacting the heating block and eliminate the need of using a second heating block in the second wire bonding process of the prior art, thereby saving time and costs in a fabrication process. Also, as positions where the first and second bonding wires are bonded to the leads on opposite sides of the leadframe correspond with each other, the conventional problems of adversely affected electrical performance and electrical mismatch can be prevented.
摘要翻译：提出了一种多芯片堆叠结构及其制造方法，包括提供具有芯片基底和多个引线的引线框架，并分别在模具基座的两个表面上设置第一和第二芯片; 将引线框架布置在具有引线接合工艺中的空腔的加热块上，第二芯片容纳在加热块的空腔中; 执行第一引线接合工艺，以通过多个第一接合线将第一芯片电连接到引线，以及在与第一接合线连接的引线的一侧上形成凸块; 通过第一芯片和第一接合线容纳在加热块的空腔中，通过凸块将引线框倒置放置到加热块，以及执行第二引线接合处理，以通过多个第二接合线将所述第二芯片电连接到所述引线。凸块用于将引线支撑到一定高度，以便使接合线不会接触加热块，并且在现有技术的第二引线接合过程中不需要使用第二加热块，从而节省了时间和成本在制造过程中。此外，由于第一和第二接合线与引线框架的相对侧上的引线接合的位置彼此对应，可以防止电性能和电不匹配受到不利影响的常规问题。

5. 发明申请

US20080251910A1 Fabricating method of semiconductor package and heat-dissipating structure applicable thereto 审中-公开
标题翻译：适用于其的半导体封装和散热结构的制造方法
公开(公告)号：US20080251910A1
公开(公告)日：2008-10-16
申请号：US12082718
申请日：2008-04-11
申请人： Chih-Wei Chang , Ho-Yi Tsai , Chien-Ping Huang , Chun-Ming Liao , Cheng-Hsu Hsiao
发明人： Chih-Wei Chang , Ho-Yi Tsai , Chien-Ping Huang , Chun-Ming Liao , Cheng-Hsu Hsiao
IPC分类号： H01L23/36 , H01L21/56
CPC分类号： H01L21/56 , H01L23/4334 , H01L2224/73253 , H01L2924/01019 , H01L2924/01079
摘要： A method for fabricating semiconductor packages is disclosed, including mounting and electrically connecting a semiconductor chip onto a chip carrier; mounting a heat-dissipating structure on the semiconductor chip; placing the heat-dissipating structure into a mold cavity for filling therein a packaging material to form an encapsulant, wherein the heat-dissipating structure has a heat spreader having a size larger than that of the predetermined size of the semiconductor package, a covering layer formed on the, and a plurality of protrusions formed on edges of the covering layer that are free from being corresponding in position to the semiconductor chip, such that the protrusions can abut against a top surface of the mold cavity to prevent the heat spreader from being warped; and finally performing a singulation process according to the predetermined size and removing the encapsulant formed on the covering layer to form the desired semiconductor package. Also, this invention discloses a heat-dissipating structure applicable to the method described above.
摘要翻译：公开了一种用于制造半导体封装的方法，包括将半导体芯片安装并电连接到芯片载体上; 在半导体芯片上安装散热结构; 将散热结构放置在模腔中，用于在其中填充包装材料以形成密封剂，其中散热结构具有尺寸大于半导体封装的预定尺寸的散热器，形成覆盖层以及在覆盖层的边缘上形成的多个突起，其不与半导体芯片的位置相对应，使得突起可抵靠模腔的顶表面以防止散热器翘曲 ; 最后按照规定的尺寸进行分割处理，除去覆盖层上形成的密封剂，形成所需的半导体封装。此外，本发明公开了一种适用于上述方法的散热结构。

6. 发明申请

US20080122070A1 Heat dissipating semiconductor package and fabrication method therefor 审中-公开
标题翻译：散热半导体封装及其制造方法
公开(公告)号：US20080122070A1
公开(公告)日：2008-05-29
申请号：US11986359
申请日：2007-11-21
申请人： Wen-Tsung Tseng , Ho-Yi Tsai , Chien-Ping Huang , Chih-Wei Chang , Cheng-Hsu Hsiao
发明人： Wen-Tsung Tseng , Ho-Yi Tsai , Chien-Ping Huang , Chih-Wei Chang , Cheng-Hsu Hsiao
IPC分类号： H01L23/373 , H01L21/58
CPC分类号： H01L23/3128 , H01L21/568 , H01L23/4334 , H01L24/16 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/16152 , H01L2224/0401
摘要： A heat dissipating semiconductor package and a fabrication method therefor are provided. The fabrication method for the heat dissipating semiconductor package mainly includes steps of: containing a substrate having a chip mounted thereon in an aperture of a carrier; mounting a heat dissipating sheet having supporting portions on the carrier with the heat dissipating sheet being attached on the chip; forming an encapsulant to encapsulate the semiconductor chip and the heat dissipating structure; removing a part of the encapsulant above the heat dissipating sheet with a part of the heat dissipating sheet exposed from the encapsulant by lapping; and forming a cover layer on the part of heat dissipating sheet to prevent it from oxidation; and cutting along a predetermined size of the semiconductor package, thereby heat generated from an operation of the chip is dissipated via the heat dissipating structure.
摘要翻译：提供一种散热半导体封装及其制造方法。用于散热半导体封装的制造方法主要包括以下步骤：将载置有孔的芯片安装在其上; 将散热板安装在载体上，并将散热板安装在芯片上; 形成密封剂以封装半导体芯片和散热结构; 通过研磨从所述密封剂暴露出的部分所述散热片去除所述散热片上方的所述密封剂的一部分; 在散热片的一部分上形成覆盖层以防止其氧化; 并且沿着预定尺寸的半导体封装进行切割，由此从芯片的操作产生的热量经由散热结构消散。

7. 发明申请

US20070138632A1 Electronic carrier board and package structure thereof 审中-公开
标题翻译：电子载板及其封装结构
公开(公告)号：US20070138632A1
公开(公告)日：2007-06-21
申请号：US11642439
申请日：2006-12-19
申请人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Fang-Lin Tsai , Ho-Yi Tsai , Chih-Ming Huang , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L23/34
CPC分类号： H05K3/3452 , H05K3/284 , H05K3/303 , H05K2201/0989 , H05K2201/10636 , H05K2201/10727 , H05K2201/2036 , Y02P70/611 , Y02P70/613
摘要： An electronic carrier board and a package structure thereof are provided. The electronic carrier board includes a carrier, at least one pair of bond pads formed on the carrier, and a protective layer covering the carrier. An opening is formed in the protective layer to expose at least three sides of each of the paired bond pads. The protective layer includes at least one independent residual portion located in the opening and between the paired bond pads, such that an electronic component is mounted on the independent residual portion and electrically connected to the bond pads. A groove without a dead space is formed between the electronic component and the carrier, such that a molding compound for encapsulating the electronic component can flow through the groove to fill the opening and a space under the electronic component and encapsulate the at least three sides of each of the bond pads.
摘要翻译：提供电子载体板及其封装结构。电子载板包括载体，形成在载体上的至少一对接合焊盘和覆盖载体的保护层。在保护层中形成开口以暴露每个配对接合焊盘的至少三个侧面。保护层包括至少一个独立的残留部分，位于开口内和成对的接合焊盘之间，使得电子部件安装在独立的残留部分上并电连接到接合焊盘。在电子部件和载体之间形成没有死空间的凹槽，使得用于封装电子部件的模制化合物可以流过凹槽以填充开口和电子部件下方的空间，并将至少三个侧面每个接合垫。

8. 发明授权

US07608915B2 Heat dissipation semiconductor package 有权
标题翻译：散热半导体封装
公开(公告)号：US07608915B2
公开(公告)日：2009-10-27
申请号：US12151902
申请日：2008-05-08
申请人： Chun-Ming Liao , Chien-Ping Huang , Ho-Yi Tsai , Cheng-Hsu Hsiao
发明人： Chun-Ming Liao , Chien-Ping Huang , Ho-Yi Tsai , Cheng-Hsu Hsiao
IPC分类号： H01L23/495 , H01J23/10
CPC分类号： H01L23/4334 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A heat dissipation semiconductor package includes a chip carrier, a semiconductor chip, a heat conductive adhesive, a heat dissipation member, and an encapsulant. The semiconductor chip is flip-chip mounted on the chip carrier and defined with a heat conductive adhesive mounting area. Periphery of the heat adhesive mounting area is spaced apart from edge of the semiconductor chip. The heat dissipation member is mounted on the heat conductive adhesive formed in the heat conductive adhesive mounting area. The encapsulant formed between the chip carrier and the heat dissipation member encapsulates the semiconductor chip and the heat conductive adhesive, and embeds edges of the active surface and non-active surface and side edge of the semiconductor chip, thereby increasing bonding area between the encapsulant and the semiconductor chip. The side edges of the heat conductive adhesive and the semiconductor chip are not flush with each other, thereby preventing propagation of delamination.
摘要翻译：散热半导体封装包括芯片载体，半导体芯片，导热粘合剂，散热构件和密封剂。半导体芯片倒装芯片安装在芯片载体上，并用导热粘合剂安装区域限定。热粘合剂安装区域的周边与半导体芯片的边缘间隔开。散热构件安装在形成在导热粘合剂安装区域中的导热粘合剂上。形成在芯片载体和散热构件之间的密封剂封装半导体芯片和导热粘合剂，并且嵌入半导体芯片的有源表面和非有源表面和侧边缘的边缘，从而增加密封剂和半导体芯片。导热粘合剂和半导体芯片的侧边缘彼此不齐平，从而防止分层的蔓延。

9. 发明申请

US20080122071A1 Heat dissipating semiconductor package and fabrication method therefor 审中-公开
标题翻译：散热半导体封装及其制造方法
公开(公告)号：US20080122071A1
公开(公告)日：2008-05-29
申请号：US11986362
申请日：2007-11-21
申请人： Wen-Tsung Tseng , Ho-Yi Tsai , Chien-Ping Huang , Chih-Wei Chang , Cheng-Hsu Hsiao
发明人： Wen-Tsung Tseng , Ho-Yi Tsai , Chien-Ping Huang , Chih-Wei Chang , Cheng-Hsu Hsiao
IPC分类号： H01L23/373
CPC分类号： H01L23/3128 , H01L21/568 , H01L23/4334 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253 , H01L2924/15311
摘要： A heat dissipating semiconductor package and the fabrication method therefor are provided. The fabrication method for the heat dissipating semiconductor package mainly includes steps of: containing a substrate having a chip mounted thereon in an aperture of a carrier, wherein the carrier has an electroconductive layer; allowing a heat dissipating structure having supporting portions to be mounted on and electrically connected to the electroconductive layer of the carrier via the supporting portions thereof while heat dissipating structure being mounted on the chip; after an encapsulation process and removing a part of the encapsulant above the heat dissipating sheet by lapping to expose a surface of the heat dissipating structure from the encapsulant, depositing and forming a metal passivation layer on the surface of the heat dissipating structure by electroplating for preventing the heat dissipating structure from oxidizing.
摘要翻译：提供一种散热半导体封装及其制造方法。用于散热半导体封装的制造方法主要包括以下步骤：在载体的孔中容纳其上安装有芯片的基板，其中载体具有导电层; 允许散热结构，其具有支撑部分，其安装在载体的导电层上并通过其支撑部分电连接，同时散热结构安装在芯片上; 在封装工艺之后并且通过研磨去除散热片上方的一部分密封剂，以从密封剂暴露出散热结构的表面，在散热结构的表面上沉积和形成金属钝化层，通过电镀防止散热结构从氧化。

10. 发明授权

US07348211B2 Method for fabricating semiconductor packages 有权
标题翻译：半导体封装的制造方法
公开(公告)号：US07348211B2
公开(公告)日：2008-03-25
申请号：US11117158
申请日：2005-04-27
申请人： Ying-Ren Lin , Ho-Yi Tsai , Chien-Ping Huang , Cheng-Hsu Hsiao
发明人： Ying-Ren Lin , Ho-Yi Tsai , Chien-Ping Huang , Cheng-Hsu Hsiao
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44
CPC分类号： H01L21/565 , H01L21/568 , H01L23/3128 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for fabricating semiconductor packages is proposed. A plurality of substrates each having a chip thereon are prepared. Each substrate has similar length and width to the predetermined length and width of the semiconductor package. A carrier having a plurality of openings is prepared. Each opening is larger in length and width than the substrate. The substrates are positioned in the corresponding openings, and gaps between the substrates and the carrier are sealed. A molding process is performed to form an encapsulant over each opening to encapsulate the chip. An area on the carrier covered by the encapsulant is larger in length and width than the opening. After performing a mold-releasing process, a plurality of the semiconductor packages are formed by a singulation process to cut along substantially edges of each substrate according to the predetermined size of the semiconductor package. A waste of substrate material is avoided.
摘要翻译：提出了制造半导体封装的方法。制备各自具有芯片的多个基板。每个衬底具有与半导体封装的预定长度和宽度相似的长度和宽度。制备具有多个开口的载体。每个开口的长度和宽度大于衬底。基板定位在相应的开口中，基板和载体之间的间隙被密封。执行成型工艺以在每个开口上形成密封剂以封装芯片。由密封剂覆盖的载体上的区域的长度和宽度大于开口的宽度。在执行脱模工艺之后，通过单片化工艺形成多个半导体封装，以根据半导体封装的预定尺寸沿着每个衬底的大致边缘切割。避免了衬底材料的浪费。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式