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1. 发明授权

US4864558A Self-routing switch 失效
标题翻译：自动路由交换机
公开(公告)号：US4864558A
公开(公告)日：1989-09-05
申请号：US121967
申请日：1987-11-17
申请人： Hitoshi Imagawa , Shigeo Urushidani , Koichi Hagishima
发明人： Hitoshi Imagawa , Shigeo Urushidani , Koichi Hagishima
IPC分类号： H04L12/931 , H04L12/937 , H04L12/947
CPC分类号： H04L49/25 , H04L49/254 , H04L49/40
摘要： In a self-routing switch which comprises a plurality of switching stages inserted between pluralities of input and output lines and cascade-connected by pluralities of input and output links, each switching stage includes a plurality of cascade-connected store/switch elements. Each store/switch element of each switching stage outputs an information data input thereto from the corresponding input link to the corresponding output link or shifts the input information data through a predetermined number of cascade-connected elements and outputs it to the corresponding output link, in accordance with a portion of routing information contained in the input information data, which portion corresponds to the switching stage.
摘要翻译：在包括多个输入和输出线之间插入并由多个输入和输出链路级联连接的多个开关级的自路由开关中，每个开关级包括多个级联连接的存储/开关元件。每个切换级的每个存储/切换元件从相应的输入链路将输入的信息数据输出到对应的输出链路，或者通过预定数量的级联连接的元件移位输入信息数据，并将其输出到相应的输出链路，根据包含在输入信息数据中的路由信息的一部分，该部分对应于切换阶段。

2. 发明授权

US5022025A Self-routing switch and its routing method 失效
标题翻译：自路由交换机及其路由方法
公开(公告)号：US5022025A
公开(公告)日：1991-06-04
申请号：US309647
申请日：1989-02-13
申请人： Shigeo Urushidani , Hitoshi Imagawa
发明人： Shigeo Urushidani , Hitoshi Imagawa
IPC分类号： H04Q3/00 , H04L12/20 , H04L12/931
CPC分类号： H04L49/256 , H04L49/101 , H04L49/106 , H04L49/1553 , H04L49/255
摘要： A self-routing switch in which a plurality of switching stages, each having a plurality of switching elements, are sequentially connected by substitute links, wherein additional two input terminals and additional two output terminals are provided in each switching element of at least the last plural switching stages of the switch, and the output terminals and input terminals of the same line position between these last plural switching stages are connected by equivalent links, respectively. When information data appended with a destination address and judge times, as routing information, is input into the switch, one of the bits in the destination address is selected as a judge bit on the basis of the judge times, and the output terminal to which the information data is to be output is selected according to the value of the judge bit.

3. 发明授权

US4245325A Digital multifrequency signalling receiver 失效
标题翻译：数字多频信令接收机
公开(公告)号：US4245325A
公开(公告)日：1981-01-13
申请号：US12507
申请日：1979-02-15
申请人： Shiro Kikuchi , Hitoshi Imagawa , Yasumasa Iwase
发明人： Shiro Kikuchi , Hitoshi Imagawa , Yasumasa Iwase
IPC分类号： H04Q1/457 , G06F15/31
CPC分类号： H04Q1/457
摘要： Disclosed is a digital multifrequency signaling receiving system in which a first operation device executes an operation to multiply multifrequency signals composed of N samples as input signals by a window function including coefficients required for fast Fourier transform. An output produced at the first operation device, as a sample signal, is subjected to fast Fourier transformation at a second operation device which includes a subtractor and a logic circuit. In the subtractor, the sample signals are delayed N/2 samples to halve the number of sample signals. The logic circuit executes an operation for the sample signals, taking advantage of the fact that some frequencies of the outputs of the Fourier transform are represented as the conjugate complex of the other outputs of the Fourier transform. The sample signals fast-Fourier-transformed and produced at the second operation device are subjected discrete Fourier transformation in a processor, where an output for detecting the multifrequency signals is obtained.
摘要翻译：公开了一种数字多频信号接收系统，其中第一操作装置执行将由N个采样构成的多频信号乘以包括快速傅里叶变换所需的系数的窗函数作为输入信号的操作。在第一操作装置处产生的作为采样信号的输出在包括减法器和逻辑电路的第二操作装置上进行快速傅里叶变换。在减法器中，采样信号是延迟的N / 2采样，将采样信号的数量减半。利用傅里叶变换的输出的一些频率表示为傅里叶变换的其他输出的共轭复合的事实，逻辑电路对采样信号执行操作。在第二操作装置中快速傅立叶变换和产生的样本信号在处理器中进行离散傅里叶变换，其中获得用于检测多频信号的输出。

4. 发明授权

US5594724A Transmission convergence sublayer multiplex generating/terminating apparatus 失效
标题翻译：发送汇聚子层复用生成/终端装置
公开(公告)号：US5594724A
公开(公告)日：1997-01-14
申请号：US522555
申请日：1995-09-01
申请人： Masao Akata , Takao Miura , Takeshi Ogawa , Yukihiro Doi , Isao Higashi , Hitoshi Imagawa
发明人： Masao Akata , Takao Miura , Takeshi Ogawa , Yukihiro Doi , Isao Higashi , Hitoshi Imagawa
IPC分类号： H04Q3/00 , H04J3/00 , H04J3/16 , H04L12/64 , H04L12/951 , H04Q11/04 , H04L12/66
CPC分类号： H04Q11/0478 , H04J3/1611 , H04J2203/0089 , H04L2012/5647 , H04L2012/5673
摘要： A transmission convergence sublayer multiplex generating apparatus includes a TC layer calculating section, a TC layer information storing section for storing TC layer information in correspondence with each path, and an ATM layer information storing section for storing ATM layer information in correspondence with each path. The TC layer calculating section includes a section for, when receiving an ATM layer cell, storing the ATM layer cell in the ATM layer information storing section corresponding to a path number on the basis of header information of the ATM layer cell, and for, when receiving a TC layer information read request for each path through a control line, generating header error control information and scrambling the payload portion by time division multiplex processing using the ATM layer information of the corresponding path which is stored in the ATM layer information storing section to generate TC layer information, storing the TC layer information in the TC layer information storing section of the corresponding path, and outputting the TC layer information of the corresponding path to the TC layer information output line. A transmission convergence sublayer multiplex terminating apparatus is also disclosed.
摘要翻译：发送汇聚子层多路复用生成装置包括：TC层计算部，与每个路径对应地存储TC层信息的TC层信息存储部，以及与各路对应地存储ATM层信息的ATM层信息存储部。 TC层计算部分包括一个部分，用于当接收到一个ATM层信元时，根据ATM层信元的报头信息将ATM层信元存储在与ATM数据信道对应的ATM层信息存储部分中，通过控制线路接收每个路径的TC层信息读取请求，通过使用存储在ATM层信息存储部分中的对应路径的ATM层信息的时分多路复用处理产生报头错误控制信息和加扰有效负载部分，生成TC层信息，将TC层信息存储在对应路径的TC层信息存储部中，并将对应路径的TC层信息输出到TC层信息输出行。还公开了一种传输汇聚子层复用终端设备。

5. 发明授权

US4328398A Digital multi-frequency receiver 失效
标题翻译：数字多频接收机
公开(公告)号：US4328398A
公开(公告)日：1982-05-04
申请号：US148232
申请日：1980-05-09
申请人： Masaharu Kawaguchi , Yoshikatu Shiraishi , Kazuhiro Maruyama , Hitoshi Imagawa , Yoshimasa Kaneko
发明人： Masaharu Kawaguchi , Yoshikatu Shiraishi , Kazuhiro Maruyama , Hitoshi Imagawa , Yoshimasa Kaneko
IPC分类号： H04Q1/457 , H04M1/50
CPC分类号： H04Q1/4575
摘要： A digital multi-frequency receiver for the use in an electronic telephone exchange system for detecting MF signals (700,900, 1100, 1300, 1500 and 1700 Hz) in the CCITT No. 5 system. The digital multi-frequency receiver comprises a recursive digital filter for detecting each of the MF signals on a time divisional basis, an absolute value circuit for providing the absolute value of the output of the recursive digital filter, a comparator for comparing the output of the absolute value circuit with a variable threshold to provide the detected MF signal information, and a circuit for providing the variable threshold by selecting the maximum value from among, (i) the predetermined fixed value, (ii) the product of the value .alpha. which is less than but close to 1 and the maximum value of the variable threshold circuit in a preceding frame, and (iii) the maximum value of the output of the absolute value circuit in a present frame.
摘要翻译：一种用于电子电话交换系统中用于检测CCITT 5系统中的MF信号（700,900,1100,1300,1500和1700Hz）的数字多频接收机。数字多频接收机包括用于基于时分检测每个MF信号的递归数字滤波器，用于提供递归数字滤波器的输出的绝对值的绝对值电路，用于将递归数字滤波器的输出进行比较的比较器具有可变阈值以提供检测到的MF信号信息的绝对值电路，以及用于通过从（i）预定固定值中选择最大值来提供可变阈值的电路，（ii）值α的乘积，小于但接近1，并且前一帧中的可变阈值电路的最大值，以及（iii）当前帧中的绝对值电路的输出的最大值。

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