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    • 2. 发明授权
    • Motor with integral bracket brush holder
    • 电机带一体式支架刷架
    • US4673836A
    • 1987-06-16
    • US765365
    • 1985-08-13
    • Tsutomu AkiyamaToshiyuki Kobayashi
    • Tsutomu AkiyamaToshiyuki Kobayashi
    • H01R39/38H01R39/40H02K5/14H02K5/15H02K13/00H02K5/16H02K15/00
    • H01R39/40H02K5/148H02K5/15
    • A revolving electric machine wherein a brush holder formed of resin is solidly secured to a bracket and this bracket is jointed to an opening of a yoke. The bracket is formed into a thin plate shape. A portion of the bracket is clamped from the opposite side by a resin material of the brush holder, whereby the bracket is integrally formed with the brush holder. A faucet joint portion of the brush holder is formed when the brush holder is formed of resin and the faucet joint portion is faucet-jointed to the opening of the yoke, whereby the bracket is center-aligned with the yoke. One of the terminals of a brush penetrates through a resin material of the brush holder and is extracted to the outside. The outer of the terminals of the brush is connected to the outside of the bracket.
    • 一种旋转电机,其中由树脂形成的刷架牢固地固定到支架上,并且该支架接合到轭的开口。 支架形成为薄板形状。 支架的一部分由电刷架的树脂材料从相对侧夹紧,由此支架与电刷架一体地形成。 当电刷架由树脂形成时,电刷架的水龙头接合部分形成,并且水龙头接头部分与磁轭的开口水龙头接合,从而托架与轭架对中。 刷子的一个端子穿过电刷架的树脂材料并被抽出到外部。 刷子的端子的外部连接到支架的外部。
    • 5. 发明授权
    • Failure self-diagnosis device for semiconductor memory
    • 半导体存储器故障自诊断装置
    • US6009028A
    • 1999-12-28
    • US154774
    • 1998-09-17
    • Tsutomu Akiyama
    • Tsutomu Akiyama
    • G01R31/28G01R31/3193G06F11/22G06F12/16G11C29/02G11C29/12G11C29/16G11C7/00
    • G11C29/16G01R31/31935
    • The failure self-diagnosis device for semiconductor memory, comprises: a CPU for controlling a diagnosis operation; a data generating circuit for generating a test data to be written into memory elements to be diagnosed and an expected data which is the same as a data to be precisely read out from the memory elements after the test data was precisely written into the memory elements; a clock generating circuit for outputting a clock signal; address generating circuits, each of which is arranged with each of the memory elements to be diagnosed, for generating address assigning signals by synchronizing with the clock signal; comparators, each of which is arranged with each of the memory elements to be diagnosed, for comparing read out data which was read out from each of the memory elements by synchronizing with the address assigning signal, with the expected data; and diagnosis stop circuits, each of which is arranged with each of the memory elements to be diagnosed, for stopping the diagnosis operation of each of the memory elements when a corresponding comparator judges that the read out data from a corresponding memory element is not coincident with the expected data.
    • 半导体存储器的故障自诊断装置包括:用于控制诊断操作的CPU; 数据产生电路,用于在将测试数据精确地写入存储器元件之后,生成要写入待诊断的存储器元件的测试数据和与从存储器元件精确读出的数据相同的预期数据; 时钟发生电路,用于输出时钟信号; 地址发生电路,其中每个被布置成要被诊断的每个存储器元件,用于通过与时钟信号同步来产生地址分配信号; 比较器,其中每个被布置为要被诊断的每个存储器元件,用于将从每个存储器元件读出的读出数据与地址分配信号同步地与预期数据进行比较; 以及诊断停止电路,每个诊断停止电路配置有要被诊断的每个存储器元件,用于当相应的比较器判断出来自相应的存储器元件的读出数据不一致时停止每个存储器元件的诊断操作 预期数据。
    • 7. 发明授权
    • Nerve regeneration promoters
    • 神经再生促进剂
    • US08569058B2
    • 2013-10-29
    • US10574479
    • 2004-10-01
    • Narito TateishiJunki YamamotoSoichi KawaharadaTsutomu AkiyamaMasamitsu Hoshikawa
    • Narito TateishiJunki YamamotoSoichi KawaharadaTsutomu AkiyamaMasamitsu Hoshikawa
    • C12N5/00C12N5/02
    • A61K31/20A61K31/19A61K45/06
    • A nerve regeneration which comprises a compound is represented by formula (I): (wherein all symbols are shown in the description), a salt thereof or a prodrug thereof. The compound of the present invention is suppresses nerve cell death as a substance for accelerating growth and/or differentiation of stem cells (nerve stem cells, embryonic stem cells, bone marrow cells, etc.), a substance for accelerating growth and/or differentiation of nerve precursor cells, a potentiator for neurotrophic factor activity, a neurotrophic factor-like substance or a neurodegenerative suppressor, and accelerates repair and regeneration of nerve tissues by neogenesis, regeneration and/or axon evolution. In addition, the compound of the present invention is useful for preparation from brain tissues, bone marrow and/or embryonic stem cells of cells for transplant (nerve stem cells, nerve precursor cells, nerve cells, etc.) and also accelerates grafting, growth, differentiation and/or function expression of cells for transplant whereupon it is useful for prevention and/or treatment of neurodegenerative diseases.
    • 包含化合物的神经再生由式(I)表示:(其中所有符号在说明书中显示),其盐或其前药。 本发明的化合物抑制作为加速生长和/或分化的干细胞(神经干细胞,胚胎干细胞,骨髓细胞等)的生长和/或分化的物质的神经细胞死亡 的神经前体细胞,神经营养因子活性的增强剂,神经营养因子样物质或神经变性抑制剂,并通过新生,再生和/或轴突进化加速神经组织的修复和再生。 此外,本发明的化合物可用于从用于移植的细胞(神经干细胞,神经前体细胞,神经细胞等)的脑组织,骨髓和/或胚胎干细胞制备,并且还加速接枝,生长 ,用于移植的细胞的分化和/或功能表达,因此它可用于预防和/或治疗神经变性疾病。
    • 10. 发明授权
    • Self-diagnostic device for semiconductor memories
    • 用于半导体存储器的自诊断装置
    • US5561671A
    • 1996-10-01
    • US545314
    • 1995-10-19
    • Tsutomu Akiyama
    • Tsutomu Akiyama
    • G01R31/28G11C29/10G11C29/18G11C29/36G11C29/00G06F11/00
    • G11C29/36G11C29/18
    • A self-diagnostic device for checking the performance of memory matrix in semiconductor devices is presented. The device is applicable particularly to those IC testers having high bit and high capacity memories. The device is capable of performing march and checker tasks simultaneously. The program data contained in a CPU 1 are written into the memory matrix 5 by way of the data generation circuit 2 and the address generation circuit 3. The test data are entered into a comparator 4 at the timing governed by the clock generation circuit 6, and are compared with the expected data from the data generation circuit 2. When there is a non-coincidence, a defect signal is generated from a flip-flop (FF) circuit 9. In the present device, the conventional division circuits are replaced by two FF circuits 8, 9, and two EOR-gates 11, 12 and associated components to provide simplicity in circuit configuration and efficient operation while retaining the advantages offered by the conventional march- and checker-modes. The FF circuit 8 provides a set/reset-signal in response to a clock signal from the clock generation circuit 6. The EOR-gate 12 operates so as to generate an inverted signal of the lowermost bit A0 of either the output data from the FF circuit 8 or from the address generation circuit 3. The EOR-gate 11 generates inverted signals of the output data from the data generation circuit 2 upon receiving a signal from the EOR-gate 12.
    • 介绍了一种用于检查半导体器件中存储矩阵性能的自诊断设备。 该器件特别适用于具有高位和高容量存储器的那些IC测试仪。 该设备能够同时执行行军和检查任务。 包含在CPU 1中的程序数据通过数据产生电路2和地址生成电路3写入存储矩阵5.测试数据在由时钟产生电路6控制的定时输入到比较器4中, 并且与来自数据生成电路2的期望数据进行比较。当存在不一致时,从触发器(FF)电路9产生缺陷信号。在本装置中,将传统的除法电路替换为 两个FF电路8,9和两个EOR门11,12以及相关联的部件,以提供简单的电路配置和有效的操作,同时保持传统的行进和检验模式所提供的优点。 FF电路8响应于来自时钟发生电路6的时钟信号而提供置位/复位信号.EOR门12进行工作,以产生来自FF的输出数据的最低位A0的反相信号 电路8或来自地址产生电路3.EOR门11在从EOR门12接收到信号时,从数据产生电路2产生输出数据的反相信号。