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1. 发明授权

US5490041A Semiconductor integrated circuit module and a semiconductor integrated circuit device stacking the same 失效
标题翻译：半导体集成电路模块和集成电路的半导体集成电路器件
公开(公告)号：US5490041A
公开(公告)日：1996-02-06
申请号：US222487
申请日：1994-04-04
申请人： Hitonobu Furukawa , Hayami Matsunaga , Yoshikazu Suehiro , Masao Iwata , Takeo Yasuho , Izumi Okamoto , Kazuo Takeda , Shuji Ida
发明人： Hitonobu Furukawa , Hayami Matsunaga , Yoshikazu Suehiro , Masao Iwata , Takeo Yasuho , Izumi Okamoto , Kazuo Takeda , Shuji Ida
IPC分类号： H01L25/18 , H01L25/04 , H01L25/065 , H01L25/10 , H01L25/11 , H05K7/02 , H05K7/06
CPC分类号： H05K7/023 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2225/06551 , H01L2225/06579 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H01L2924/1627 , H01L2924/3011
摘要： A plurality of memory modules are stacked so as to form a multilayer integrated memory circuit. All of the memory modules have a plurality of bare memory IC chips mounted thereon, and have the same structure, the same circuit configuration and the same terminal arrangement in lead frames with each other. Each of the memory modules to be stacked in each layer is rotated by 90.degree., 180.degree. or 270.degree. before being stacked and connected to each other. Thus, in the multi-layered memory circuit, it is possible that signals can be selectively input/output to/from a particular layer in the multilayer structure, although the lead terminals of each of memory modules has the same configuration and the same arrangement with each other. As a result, a small-size integrated memory circuit device with a large memory-capacity can be provided, which can be fabricated easily and efficiently. A higher processing speed of digital computers can be also achieved.
摘要翻译：堆叠多个存储器模块以形成多层集成存储器电路。所有存储器模块具有安装在其上的多个裸存储器IC芯片，并且具有与引线框架相同的结构，相同的电路结构和相同的端子布置。堆叠在每个层中的每个存储模块在堆叠并相互连接之前旋转90°，180°或270°。因此，在多层存储器电路中，虽然各存储器模块的引线端子具有相同的结构和相同的配置，但是与多层结构中的特定层可以选择性地输入/输出信号彼此。结果，可以提供容易且有效地制造的具有大的存储容量的小尺寸集成存储器电路器件。也可以实现数字计算机的更高的处理速度。

2. 发明授权

US5528458A Integrated circuit device and its manufacturing method 失效
标题翻译：集成电路器件及其制造方法
公开(公告)号：US5528458A
公开(公告)日：1996-06-18
申请号：US344693
申请日：1994-11-18
申请人： Takeo Yasuho , Hayami Matunaga , Masao Iwata , Hitonobu Furukawa
发明人： Takeo Yasuho , Hayami Matunaga , Masao Iwata , Hitonobu Furukawa
IPC分类号： H01L23/12 , H01L21/58 , H01L23/31 , H01L23/498 , H05K7/20
CPC分类号： H01L24/83 , H01L23/3135 , H01L23/49811 , H01L23/4985 , H01L24/29 , H01L2224/16 , H01L2224/2919 , H01L2224/73265 , H01L2224/8319 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/09701 , H01L2924/14 , H01L2924/1532 , H01L2924/181
摘要： An integrated circuit device is disclosed that comprises a bare integrated circuit chip, having an integrated circuit section and pad sections, said chip being mounted on an insulated surface of a substrate, and an electro-conductive circuit pattern wiring formed on said insulating surface along the periphery of said chip. Tape automated bonding wiring is used to electrically connect the pad sections of the chip to an end of the circuit pattern wiring. Terminals are electrically connected to the other end of the circuit pattern wiring for use in electrically connecting the integrated circuit device to electronic equipment.
摘要翻译：公开了一种集成电路器件，其包括裸集成电路芯片，具有集成电路部分和焊盘部分，所述芯片安装在基板的绝缘表面上，以及形成在所述绝缘表面上的导电电路图案布线沿着所述芯片的外围。磁带自动接合线用于将芯片的焊盘部分电连接到电路图案布线的一端。端子电连接到电路图案布线的另一端，用于将集成电路器件电连接到电子设备。

3. 发明授权

US06996388B2 High-frequency signal receiver 失效
标题翻译：高频信号接收机
公开(公告)号：US06996388B2
公开(公告)日：2006-02-07
申请号：US10109742
申请日：2002-03-28
申请人： Hiroaki Ozeki , Hitonobu Furukawa , Masanori Suzuki , Sanae Asayama , Masashi Yasuda
发明人： Hiroaki Ozeki , Hitonobu Furukawa , Masanori Suzuki , Sanae Asayama , Masashi Yasuda
IPC分类号： H04B1/26
CPC分类号： H04B1/28
摘要： A receiver is operable even if including a local oscillator generating a signal at high frequencies but not in a wide frequency range. The receiver includes: a first frequency converter for mixing a received signal with a first local oscillation signal to convert the received signal into respective signals of plural first intermediate frequencies corresponding to a frequency of the received signal; and a second frequency converter for converting the signals of the first intermediate frequencies into a signal of a second intermediate frequency.
摘要翻译：即使包括本地振荡器在高频而不是在宽的频率范围内产生信号，接收机也是可操作的。接收机包括：第一频率转换器，用于将接收信号与第一本地振荡信号混频，以将接收的信号转换成对应于接收信号的频率的多个第一中频的相应信号; 以及第二频率转换器，用于将第一中频的信号转换为第二中频信号。

4. 发明授权

US06389082B1 Receiver 有权
标题翻译：接收器
公开(公告)号：US06389082B1
公开(公告)日：2002-05-14
申请号：US09612040
申请日：2000-07-07
申请人： Masami Takigawa , Hitonobu Furukawa , Akira Mishima , Hiroaki Ozeki
发明人： Masami Takigawa , Hitonobu Furukawa , Akira Mishima , Hiroaki Ozeki
IPC分类号： H04L2706
CPC分类号： H04L27/2273 , H04L2027/0071
摘要： In a receiver supporting multiple data rates, a sweep control range is calculated on the basis of the data rate of the carrier of the channel to be selected and sweep control is executed on the oscillated frequency by VCO 8 within the sweeping frequency range so that synchronization locking to the carrier is attained and thereby an erroneous channel selection is prevented.
摘要翻译：在支持多个数据速率的接收机中，基于要选择的信道的载波的数据速率来计算扫描控制范围，并且通过VCO 8在扫频范围内对振荡频率进行扫描控制，使得同步锁定到载体，从而防止错误的通道选择。

5. 发明授权

US06363126B1 Demodulator 失效
标题翻译：解调器
公开(公告)号：US06363126B1
公开(公告)日：2002-03-26
申请号：US09209734
申请日：1998-12-11
申请人： Hitonobu Furukawa , Masami Takigawa , Akira Mishima , Hiroaki Ozeki , Sachiko Hayashi
发明人： Hitonobu Furukawa , Masami Takigawa , Akira Mishima , Hiroaki Ozeki , Sachiko Hayashi
IPC分类号： H04L2706
CPC分类号： H04L27/066 , H04L27/2273 , H04L2027/0016 , H04L2027/0028 , H04L2027/0057 , H04L2027/0065
摘要： The invention presents an apparatus capable of demodulating stably if there are time-course changes in the constituent parts in a demodulator of digital modulated signal. This demodulator comprises an operator for setting the oscillation frequency of a local oscillator 2, and within a passing frequency band of a band pass filter BPF 3, the operator controls the local oscillator 2 so that the frequency of the output signal of a first mixer 1 may settle within a control band in a controllable frequency band of an AFC feedback loop composed of an orthogonal detector 4, a carrier regenerator 9, a frequency error detector 10, a frequency controller 11, a signal selector 12, a D/A converter 13, and a VCO 14, and a local carrier is issued from the local oscillator 2 to the first mixer 1.
摘要翻译：本发明提供了一种如果在数字调制信号的解调器中的组成部分存在时间间隔变化的情况下能够稳定地进行解调的装置。该解调器包括用于设置本地振荡器2的振荡频率的操作者，并且在带通滤波器BPF 3的通过频带内，操作者控制本地振荡器2，使得第一混频器1的输出信号的频率可以在由正交检测器4，载波再生器9，频率误差检测器10，频率控制器11，信号选择器12，D / A转换器13组成的AFC反馈回路的可控频带内的控制频带内和VCO14，并且本地载波从本地振荡器2发出到第一混频器1。

6. 发明授权

US06882693B2 Digital signal receiver 失效
标题翻译：数字信号接收机
公开(公告)号：US06882693B2
公开(公告)日：2005-04-19
申请号：US09735630
申请日：2000-12-14
申请人： Hiroaki Ozeki , Masami Takigawa , Hitonobu Furukawa , Junichi Fukutani , Kazuyori Domoto
发明人： Hiroaki Ozeki , Masami Takigawa , Hitonobu Furukawa , Junichi Fukutani , Kazuyori Domoto
IPC分类号： H03H17/06 , H04B1/10 , H04B1/16 , H04B1/26 , H04B7/005 , H04L27/38 , H04N5/44 , H04L27/08 , H03D1/04
CPC分类号： H04L27/3809
摘要： A digital signal receiver capable of obtaining a favorable receiving performance even if the input signal level changes rapidly is presented. A control voltage for controlling a variable gain amplifier is read by a microprocessor, and an operation-starting point of the variable gain amplifier is shifted by using this control voltage. As a result, a favorable level fluctuation response characteristic is obtained regardless of the input level.
摘要翻译：即使输入信号电平急剧变化，也能够得到良好的接收性能的数字信号接收机。用于控制可变增益放大器的控制电压由微处理器读取，并且通过使用该控制电压来移动可变增益放大器的操作起始点。结果，无论输入电平如何，都获得良好的电平波动响应特性。

7. 发明授权

US06744830B1 Digital broadcasting signal receiver 失效
标题翻译：数字广播信号接收机
公开(公告)号：US06744830B1
公开(公告)日：2004-06-01
申请号：US09670692
申请日：2000-09-28
申请人： Hitonobu Furukawa , Hiroaki Ozeki , Masami Takigawa , Junichi Fukutani , Yuichi Watanabe , Kazuyori Domoto
发明人： Hitonobu Furukawa , Hiroaki Ozeki , Masami Takigawa , Junichi Fukutani , Yuichi Watanabe , Kazuyori Domoto
IPC分类号： H04L2708
CPC分类号： H04N5/4401 , H03G3/3089 , H04H40/18 , H04L7/04 , H04N5/50 , H04N21/4384
摘要： A receiver for a digital broadcasting service have a compatibility between tuning to a desired channel at a short period of time and an improve ment of a bit error rate (BER) characteristics. In a case where a target wave is fluctuated, to prevent the receiver from having a significant declination of BER characteristics and to ensure the reproduction of high quality images, the receiver includes an automatic gain controller including a loop filter in which the frequency range of the loop filter can be switched according to an output of a synchronous state discriminator. The frequency band of the loop filter is selectively adjusted to one setting designed for minimizing the duration for tuning a desired channel before a synchronous state is established. After the synchronous state established, the frequency band of the loop filter is switched to another setting designed for enhancing BER characteristics.
摘要翻译：用于数字广播服务的接收机具有在短时间段内调谐到期望信道和提高误码率（BER）特性之间的兼容性。在目标波波动的情况下，为了防止接收机具有BER特性的显着偏差并且确保高质量图像的再现，接收机包括自动增益控制器，该自动增益控制器包括环路滤波器，其中频率范围可以根据同步状态鉴别器的输出来切换环路滤波器。环路滤波器的频带被选择性地调整为设计用于在建立同步状态之前最小化用于调谐期望信道的持续时间的一个设置。在建立同步状态之后，环路滤波器的频带被切换到另一个设计用于提高BER特性的设置。

8. 发明授权

US06272509B1 Filter device 失效
标题翻译：过滤装置
公开(公告)号：US06272509B1
公开(公告)日：2001-08-07
申请号：US09208521
申请日：1998-12-09
申请人： Hitonobu Furukawa , Hideya Kitamura , Hirokazu Kitamura , Tetsuya Fuke , Atsushi Doi
发明人： Hitonobu Furukawa , Hideya Kitamura , Hirokazu Kitamura , Tetsuya Fuke , Atsushi Doi
IPC分类号： G06F1710
CPC分类号： H03H17/0223
摘要： The invention relates to a filter device, and is intended to prevent drastic changes of output modulation signal and assures the performance as modulator if output modulation signal is transmitted and stopped frequency by using TDMA in communication control. To achieve the object, the invention comprises a shift register 1, a plurality of memories 2 connected to this shift register 1 and increased in the bit width of input address by one bit each, and a selector 3 for selecting outputs from these plurality of memories 2, in which the output of the shift register 1 is used as a higher side address of each one of the memories 2, a lower side address of each one of the memory addresses is common, the bit width of the higher side address increases by one bit each starting from one bit, and addresses are assigned sequentially from the lower side of the higher side address of the memories 2 depending on the shift from the lowest side bit of the shift register 1.
摘要翻译：本发明涉及一种滤波器装置，并且旨在防止输出调制信号的剧烈变化，并且通过在通信控制中使用TDMA来输出调制信号被发送和停止频率，确保作为调制器的性能。为了实现该目的，本发明包括移位寄存器1，连接到该移位寄存器1并且每个输入地址的位宽度增加的多个存储器2和用于选择来自这些多个存储器2的输出的选择器3，其中移位的输出寄存器1用作存储器2中的每一个的高位地址，每个存储器地址的下侧地址是公共的，高位地址的位宽从一位开始增加1位，根据从移位寄存器1的最低位开始的移位，从存储器2的较高侧地址的下侧依次分配地址。

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