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    • 3. 发明授权
    • Electric energy storage device with cell energy control, and method of controlling cell energy
    • 具有电池能量控制的蓄电装置,以及控制电池能量的方法
    • US06538414B1
    • 2003-03-25
    • US09869737
    • 2001-07-03
    • Kikuo TsurugaAkio HasebeKazuya MoriSumiko SekiTakahiko Ito
    • Kikuo TsurugaAkio HasebeKazuya MoriSumiko SekiTakahiko Ito
    • H01M1044
    • H02J7/0016
    • An energy adjusting device is provided which transfers energy charged in an arbitrary cell to the input/output terminals of a unit energy storage device. The energy adjusting device includes a transformer having a plurality of primary coils and a secondary coil mutually coupled magnetically but electrically insulated, switching circuits which open and close the circuits of the primary coils of the transformer connected to the arbitrary cell, a circuit connecting the secondary coil of the transformer via a rectifying circuit to the input/output terminals of the unit energy storage device, and a control circuit which, by operating the switching circuits, adjusts the amount of energy stored in the cells to a specific ratio with respect to the amount of energy stored by the unit energy storage device.
    • 提供了一种能量调节装置,其将在任意单元中充电的能量传送到单位能量存储装置的输入/输出端子。 能量调节装置包括具有多个初级线圈的变压器和相互耦合的电气但电绝缘的次级线圈,开关电路,其连接到任意电池的变压器的初级线圈的电路,连接二次 变压器的线圈通过整流电路连接到单元储能装置的输入/输出端子;以及控制电路,其通过操作开关电路将存储在单元中的能量的量调整到相对于 单位储能装置储存的能量。
    • 5. 发明授权
    • Contact plug forming method
    • 接触塞形成方法
    • US5607878A
    • 1997-03-04
    • US526543
    • 1995-09-12
    • Mari OtsukaTomonori KitakuraKenichi OtsukaKazuya Mori
    • Mari OtsukaTomonori KitakuraKenichi OtsukaKazuya Mori
    • H01L21/768H01L21/28
    • H01L21/76879Y10S148/017
    • An inter-level insulation film is formed on a first-level interconnection layer and part of the inter-level insulation film which lies on the first-level interconnection layer is etched to form a contact hole. After a natural oxidation film formed on the surface of part of the first-level interconnection layer which is exposed in the contact hole is removed, the resultant structure is exposed to a gas atmosphere containing halogen to purify the surface of the inter-level insulation film. After this, a contact plug is deposited and formed on the first-level interconnection layer which is exposed in the contact hole by the selective CVD method to fill in the contact hole. A second-level interconnection layer is formed on the inter-level insulation film and the first-level and second-level interconnection layers are electrically connected to each other via the contact plug.
    • 层间绝缘膜形成在一级互连层上,并且位于第一级互连层上的层间绝缘膜的一部分被蚀刻以形成接触孔。 在形成在暴露在接触孔中的一级互连层的部分表面上的自然氧化膜被除去之后,将所得结构暴露于含有卤素的气氛中,以净化层间绝缘膜的表面 。 之后,在通过选择性CVD法在接触孔中露出的第一层互连层上沉积并形成接触插塞以填充接触孔。 第二级互连层形成在层间绝缘膜上,并且第一级和第二级互连层经由接触插塞彼此电连接。
    • 8. 发明授权
    • Memory cell array architecture for random access memory device
    • 用于随机存取存储器件的存储单元阵列架构
    • US6097621A
    • 2000-08-01
    • US302645
    • 1999-05-03
    • Kazuya Mori
    • Kazuya Mori
    • G11C11/22H01L21/8242G11C5/06H01L27/108
    • H01L27/10888G11C11/22H01L27/10891
    • A memory cell array architecture (300) for memory cells having a 6F.sup.2 area, where F is a minimum feature size, is disclosed. The array architecture (300) includes active areas (302a-302n) arranged into even columns and odd columns. The active areas (302a-302n) each include a central portion (306) and are separated from one another within a column by column spacing structures (308). The active areas of even columns are offset from those of odd columns so that the central portion the even column active areas are aligned, in the row direction, with the column spacing structures of the odd columns. This arrangement allows bit line contacts (312a-312g) to be formed at the central portions with less restrictive alignment constraints. Two storage node contacts (316a-316t) are also formed to each active area (302a-302n). A novel lithography mask for improved creation of the storage node contacts is also disclosed.
    • 公开了一种用于具有6F2区域的存储单元的存储单元阵列结构(300),其中F是最小特征尺寸。 阵列架构(300)包括排列成偶数列和奇数列的有效区域(302a-302n)。 活动区域(302a-302n)各自包括中心部分(306),并且在列间隔结构(308)内彼此分离。 偶数列的有效区域与奇数列的有效区域偏移,使得偶数列有效区域的中心部分在行方向上与奇数列的列间隔结构对准。 这种布置允许位线接触(312a-312g)形成在具有较少限制性对准限制的中央部分。 两个存储节点触点(316a-316t)也形成到每个有效区域(302a-302n)。 还公开了一种用于改善存储节点接触的创建的新型光刻掩模。
    • 9. 发明授权
    • Method of manufacturing a semiconductor device having multi-layered
wiring without hillocks at the insulating layers
    • 制造具有没有小丘的多层布线的半导体器件的方法
    • US5759912A
    • 1998-06-02
    • US653904
    • 1996-05-28
    • Kazuya MoriKenichi Otsuka
    • Kazuya MoriKenichi Otsuka
    • H01L21/3205H01L21/768H01L23/52H01L21/4763
    • H01L21/76819H01L21/76838H01L21/76885Y10S438/937
    • An Al alloy interconnection layer is deposited on a silicon oxide layer, and a first carbon layer is formed on the Al alloy interconnection layer. Then, the first carbon layer and the Al alloy interconnection layer are patterned, thereby forming a first interconnection layer consisting of the Al alloy interconnection layer and the first carbon layer. Sequentially, a second carbon layer is formed on the first interconnection layer and the silicon oxide layer. The second carbon layer is entirely etched by the RIE method, thereby leaving the second carbon layer only on side surfaces of the first interconnection layer. A high temperature layer made of SiO.sub.2 is deposited on the second carbon layer, the first interconnection layer and the silicon oxide layer. Thereafter, the high temperature layer is etched back until the first carbon layer is exposed, thus being flattened. An interlayer insulating layer is deposited on the high temperature layer and the first interconnection layer.
    • 在氧化硅层上沉积Al合金配线层,在Al合金配线层上形成第一碳层。 然后,对第一碳层和Al合金配线层进行构图,形成由Al合金配线层和第一碳层构成的第一配线层。 接下来,在第一互连层和氧化硅层上形成第二碳层。 通过RIE方法完全蚀刻第二碳层,从而仅在第一互连层的侧表面上留下第二碳层。 由SiO 2制成的高温层沉积在第二碳层,第一互连层和氧化硅层上。 此后,将高温层回蚀刻直到第一碳层露出,从而变平。 在高温层和第一互连层上沉积层间绝缘层。