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1. 发明专利

JP2003059989A Method for fabricating semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2003059989A
公开(公告)日：2003-02-28
申请号：JP2001245445
申请日：2001-08-13
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： ARAUCHI KEIKO , NOZOE MARI , SUGIMOTO ARITOSHI
IPC分类号： G01B11/24 , G01B15/00 , G01N21/956 , G01N23/225 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a technology for shortening the time required for visual comparative inspection in a semiconductor device having a plurality of kinds of pattern group where the comparing pitch and comparing direction of a repetitive pattern are different from each other. SOLUTION: Comparing pitch and comparing direction are altered during a series of inspection operations where a semiconductor wafer is scanned with an electron beam by specifying regions A and B in the inspection file of a visual comparative inspection equipment and inputting the comparing pitch (first comparison pitch d1, second comparison pitch d2) and the comparing direction (X direction, Y direction) of respective regions A and B into the inspection file.
摘要翻译：要解决的问题：提供一种用于缩短具有重复图案的比较间距和比较方向彼此不同的多种图案组的半导体装置中的视觉比较检查所需的时间的技术。解决方案：通过在目视比较检查设备的检查文件中指定区域A和B并输入比较间距（第一比较间距（第一比较间距）），在通过电子束扫描半导体晶片的一系列检查操作期间，比较间距和比较方向 d1，第二比较间距d2）和各个区域A和B的比较方向（X方向，Y方向）到检查文件中。

2. 发明专利

JP2010098018A Semiconductor wafer, and method of manufacturing semiconductor integrated circuit apparatus using the same 审中-公开
标题翻译：半导体晶体管及其制造半导体集成电路装置的方法
公开(公告)号：JP2010098018A
公开(公告)日：2010-04-30
申请号：JP2008265904
申请日：2008-10-15
申请人： Hitachi Ulsi Systems Co Ltd , 株式会社日立超エル・エス・アイ・システムズ
发明人： KURODA ATSUSHI , KOKUNI MASAKI , ARAUCHI KEIKO , NANJO JUN , SAITO KOICHI
IPC分类号： H01L21/66 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor wafer and a method of manufacturing a semiconductor integrated circuit apparatus, capable of selecting cleaning and drying conditions with which the generation of watermark is reduced, in a simple manner and moreover, at low cost.
SOLUTION: In the semiconductor wafer which serves as a TEG by which a watermark can be easily detected, there are provided a first region including a first watermark detecting pattern in which the same patterns are repeated and arranged in a first direction and a second region that includes a second watermark detecting pattern, in which the same patterns are repeated and arranged in a second direction orthogonal to the first direction. A cleaning and drying condition with which the watermark becomes minimum is searched using the semiconductor wafer, and the semiconductor wafer that forms a semiconductor integrated circuit having actual circuit functions is cleaned and dried by the cleaning and drying condition.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：为了提供半导体晶片和制造半导体集成电路装置的方法，能够以简单的方式选择能够减少水印产生的清洁和干燥条件，此外，以低成本。解决方案：在用作能够容易地检测水印的TEG的半导体晶片中，提供了第一区域，其包括第一水印检测图案，其中相同的图案被重复并排列在第一方向上，并且第二区域，其包括第二水印检测图案，其中相同的图案被重复并布置在与第一方向正交的第二方向上。使用半导体晶片搜索水印变得最小的清洁和干燥条件，并且通过清洁和干燥条件清洁并干燥形成具有实际电路功能的半导体集成电路的半导体晶片。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2010067724A Plasma damage evaluating pattern and plasma damage evaluating wafer 审中-公开
标题翻译：等离子体损害评估模式和等离子体损伤评估波形
公开(公告)号：JP2010067724A
公开(公告)日：2010-03-25
申请号：JP2008231470
申请日：2008-09-09
申请人： Hitachi Ulsi Systems Co Ltd , 株式会社日立超エル・エス・アイ・システムズ
发明人： TAKASE HIROYUKI , SATO AKIRA , SAITO KOICHI , ARAUCHI KEIKO , NANJO ATSUSHI , KURODA ATSUSHI , TASAI FUMIHIRO
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a plasma damage evaluating pattern and wafer by an STI system which can stably be supplied in the future at a low cost.
SOLUTION: The plasma damage evaluating wafer has a plurality of element forming parts, disposed in a squares pattern on a surface; and one or a plurality of evaluation patterns in the element forming parts. The evaluation pattern has an active region, a dummy active region, an STI film, an insulating film and an electrode. The dummy active regions have the same structure as those of the active regions, and are disposed having given distances in an X and Y direction, respectively. The STI region is formed so as to enclose the active regions and the dummy active regions. The insulating film is formed on a surface of the active regions as a thin film, equivalent to a gate insulating film. The electrode is formed on the surface of the active regions and on a surface of the STI region.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过可以以低成本稳定地供应的STI系统来提供等离子体损伤评估图案和晶片。解决方案：等离子体损伤评估晶片具有多个元件形成部件，其在表面上以正方形图案设置; 以及元件形成部中的一个或多个评价图案。评估图案具有有源区，伪有源区，STI膜，绝缘膜和电极。虚拟有源区域具有与有源区域相同的结构，并且分别在X和Y方向上具有给定的距离。 STI区域形成为包围有源区域和虚拟有源区域。绝缘膜形成在有源区的表面上，作为薄膜，与栅极绝缘膜相当。电极形成在有源区的表面上和STI区的表面上。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009038281A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009038281A
公开(公告)日：2009-02-19
申请号：JP2007202761
申请日：2007-08-03
申请人： Hitachi Ulsi Systems Co Ltd , 株式会社日立超エル・エス・アイ・システムズ
发明人： SATO AKIRA , NANJO ATSUSHI , SAITO KOICHI , KURODA ATSUSHI , KOKUNI MASAKI , ARAUCHI KEIKO , TAKASE HIROYUKI
IPC分类号： H01L21/822 , H01C17/06 , H01L27/04
CPC分类号： H01L2224/48091 , H01L2224/48465 , H01L2224/73265 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of improving setting accuracy of a resistance value. SOLUTION: A resistor chip 1A includes a resistor 2A and electrode pads 3A and 3B for pull-out electrically connected to both ends of it. The resistor 2A is a resistor main body for setting the resistance value and is embedded inside a resistor forming groove 4a formed on an insulating film on a semiconductor substrate 5. The electrode pads 3A and 3B for pull-out are embedded inside a pad groove 4b formed on the insulating film on the semiconductor substrate 5. By forming the resistor 2A using a semiconductor process (lithography, etching and chemical-mechanical polishing or the like), the work dimension errors of the width and film thickness of the resistor 2A are reduced. Thus, the setting accuracy of the resistance value of the resistor chip 1A is improved. Also, since the resistor chip 1A can be refined, it can be highly integrated as well. Further, since a manufacturing method used in the manufacturing process of the semiconductor device is used, the reliability of the resistor chip 1A is improved as well. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供能够提高电阻值的设定精度的技术。解决方案：电阻器芯片1A包括电阻器2A和电连接到其两端的用于拉出的电极焊盘3A和3B。电阻器2A是用于设置电阻值的电阻器主体，并且被嵌入到形成在半导体衬底5上的绝缘膜上的电阻器形成槽4a内。用于拉出的电极焊盘3A和3B被嵌入在衬垫槽4b内形成在半导体基板5上的绝缘膜上。通过使用半导体工艺（光刻，蚀刻和化学机械抛光等）形成电阻器2A，电阻器2A的宽度和膜厚度的工作尺寸误差减小。因此，电阻芯片1A的电阻值的设定精度提高。此外，由于电阻芯片1A可以被精加工，所以也可以高度集成。此外，由于使用在半导体器件的制造工艺中使用的制造方法，因此电阻器芯片1A的可靠性也得到改善。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JPH09127705A PATTERN FORMING METHOD AND PRODUCTION OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH09127705A
公开(公告)日：1997-05-16
申请号：JP28508495
申请日：1995-11-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ARAUCHI KEIKO
IPC分类号： G03F7/004 , G03F7/11 , G03F7/26 , H01L21/027 , H01L21/302 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To increase and stabilize the sensitivity of a chemically amplifying resist film in a short time by supplying acid from an acid protective film deposited on a chemically amplifying resist film so as to replenish the acid which is trapped by a stabilizer in the chemically amplifying resist film. SOLUTION: A chemically amplifying positive resist film 10 is formed on a semiconductor substrate is. This positive resist consists of, for example, a material containing a novolac resin, acid producing agent, and dissolution inhibitor as the main component and contains trimethylsulfonium iodide as a stabilizer. Then an acid protective film 11 is formed on the positive resist film 10. The film 11 consists of isothianaphthene diyl sulfonate compd. and can increase the sensitivity of the positive resist film 10 for electron beams in a short time. This is because the acid trapped by trimethylsulfonium iodide in the stabilizer in the positive resist film 10 can be replenished by supplying acid from the acid protective film 11.

6. 发明专利

JPH0845811A FORMATION OF PATTERN AND MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING FORMATION OF PATTERN 失效
公开(公告)号：JPH0845811A
公开(公告)日：1996-02-16
申请号：JP17494094
申请日：1994-07-27
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ARAUCHI KEIKO , SEDO FUMIKO , KATO MAKOTO , SATO KAZUHIKO
IPC分类号： G03F7/11 , H01L21/027
摘要： PURPOSE:To prevent the chemical stability of a pattern transfer resist film from changing with the lapse of time, by depositing a protection film of an organic film made mainly of predetermined acid on the pattern transfer resist film for protecting the pattern transfer resist film. CONSTITUTION:On a wiring conductive film 2 of a semiconductor substrate 1, an electron beam photoresist film 3 for patterning the wiring conductive film 2 is deposited by a spin coat method. Then, on the electron beam photoresist film 3, a protection film 4 for protecting the electron beam photoresist film 3 from the atmosphere is deposited by the spin coat method. Thus, since the electron beam photoresist film 3 is prevented from reacting with ions in the atmosphere, the chemical stability of the electron beam photoresist film 3 can be improved. Fluctuation of the sensitivity of the electron beam photoresist film 3 can also be prevented.

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