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1. 发明专利

JP2010109112A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2010109112A
公开(公告)日：2010-05-13
申请号：JP2008279064
申请日：2008-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ITO KIYOHITO , HOSOKI KOJI , TSUNODA MASANOBU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/0657 , H01L2225/06527 , H01L2225/06572 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a highly flexible semiconductor integrated circuit as a laminated semiconductor integrated circuit that transmits information through electromagnetic coupling between inductors, which allows semiconductor chips to be laminated even when send and receive circuits have different positionings seen from a laminated direction.
SOLUTION: The semiconductor integrated circuit has first inductors to be electromagnetically coupled with transmitting circuits 110a to 110d of a first semiconductor chip 100 to be laminated and second inductors to be electromagnetically coupled with receiving circuits 210a to 210d of a second semiconductor chip 200 to be laminated, and is equipped with an interposer substrate 300 to which the first and the second inductors are electrically connected, thus enabling inter-chip communication from the first semiconductor chip 100 to the second semiconductor chip 200.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种高度柔性的半导体集成电路，作为通过电感器之间的电磁耦合传输信息的层叠半导体集成电路，这允许半导体芯片被层压，即使当发送和接收电路具有从层叠方向。解决方案：半导体集成电路具有与要层压的第一半导体芯片100的发射电路110a至110d电磁耦合的第一电感器和与第二半导体芯片200的接收电路210a至210d电磁耦合的第二电感器并且配备有第一和第二电感器电连接的插入器基板300，从而能够从第一半导体芯片100到第二半导体芯片200进行芯片间通信。版权所有：（C ）2010，JPO＆INPIT

2. 发明专利

JP2009069920A Secure data processor 有权
标题翻译：安全数据处理器
公开(公告)号：JP2009069920A
公开(公告)日：2009-04-02
申请号：JP2007234828
申请日：2007-09-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TSUNODA MASANOBU
IPC分类号： G06F21/06 , G06F21/24 , G11C11/41 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To increase tamper-resistivity by suppressing the normality of a circuit operation by changing the circuit characteristics of a specific circuit region, and making it difficult to analyze the operation. SOLUTION: This secure data processor is provided with: a circuit comprised of a semiconductor memory cell designed so that a back gate voltage can be applied from the outside to at least a portion of a transistor; and a back gate voltage control circuit for generating a back gate voltage having either of a first voltage value by which a memory cell stably operates and a second voltage value by which the memory cell does not stably operate. The back gate voltage control circuit changes the back gate voltage according to a prescribed input pattern. When the second voltage value is selected in response to an unexpected input pattern, the memory cell does not stably operate. Thus, the normal logical operation is masked, the operation is not stopped, and analysis of the operation becomes much more difficult since the memory cell operates unstably. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过改变特定电路区域的电路特性，通过抑制电路工作的正常性来增加篡改电阻率，并且难于分析操作。解决方案：该安全数据处理器具有：由半导体存储单元组成的电路，该半导体存储单元被设计成使得可以从外部向晶体管的至少一部分施加背栅电压; 以及背栅电压控制电路，用于产生具有稳定运行存储单元的第一电压值和存储单元不能稳定工作的第二电压值的背栅电压。背栅电压控制电路根据规定的输入图案改变背栅电压。当响应于意外的输入模式选择第二电压值时，存储单元不能稳定地操作。因此，正常的逻辑操作被屏蔽，操作不停止，并且操作的分析变得困难得多，因为存储单元操作不稳定。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2010015241A Super-resolution imaging device and image processing method 审中-公开
标题翻译：超分辨率成像装置和图像处理方法
公开(公告)号：JP2010015241A
公开(公告)日：2010-01-21
申请号：JP2008172432
申请日：2008-07-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： FUJIHIRA TATSU , TERADA KOICHI , TSUNODA MASANOBU
IPC分类号： G06T3/40 , G06T3/00 , H04N1/387 , H04N5/232
摘要： PROBLEM TO BE SOLVED: To provide a super-resolution device and a method thereof for effectively performing super-resolution processing even when a captured image is moving by an integral multiple of a reading interval. SOLUTION: An imaging unit 101 captures an image and reads image data from an imaging element by mixing or thinning pixels. A motion phase determination unit 104 obtains a motion phase from the motion vector of the image data, and a reading control unit 102 decides a reading position at the imaging unit 101 on the basis of the motion phase. A super-resolution processing unit 107 combines a plurality of frames to perform the super-resolution processing by using the motion vector corrected by a deviance amount of the reading position. Here, if the motion phase has no phase deviation, the control unit 102 deviates the reading position so as to cause phase deviation less than the reading interval. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种超分辨率装置及其方法，即使当捕获的图像以读取间隔的整数倍移动时，也可有效地执行超分辨率处理。解决方案：成像单元101捕获图像，并通过混合或稀疏像素从成像元件读取图像数据。运动相位确定单元104从图像数据的运动矢量中获得运动相位，并且读取控制单元102基于运动相位来确定成像单元101处的读取位置。超分辨率处理单元107组合多个帧以通过使用通过读取位置的偏差量校正的运动矢量来执行超分辨率处理。这里，如果运动相位没有相位偏差，则控制单元102偏离读取位置，从而导致小于读取间隔的相位偏差。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2006108953A Semiconductor integrated circuit and software radio equipment 有权
标题翻译：半导体集成电路和软件无线电设备
公开(公告)号：JP2006108953A
公开(公告)日：2006-04-20
申请号：JP2004290890
申请日：2004-10-04
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TANAKA HIROSHI , TSUNODA MASANOBU , MOTOMURA TETSURO , KAWABE MANABU , TAKADA MASASHI
IPC分类号： H04B1/38 , H04B7/26
CPC分类号： H04B1/0003 , H04B1/406
摘要： PROBLEM TO BE SOLVED: To provide hardware and software, which can time-divisionally process transmission, reception or synchronization and demodulation and to realize a software radio processing with a small circuit area. SOLUTION: Equipment is provided with circuit DRC which has a structure whose configuration can be changed at high speed and whose configuration can dynamically be changed, a general-purpose processor and an interface connected with an outer device such as an AD converter and a DA converter. Thus, software radio is realized by using a software radio chip where a plurality of processings such as transmission, reception, synchronization and demodulation are time-divisionally performed. Consequently, the different processings in the radio signal processings can time-divisionally be processed. Thus, software radio is realized with a circuit of the smaller area compared to a software radio system for performing the processing by allocating a region of FPGA to the respective processings. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供可以分时处理传输，接收或同步和解调的硬件和软件，并实现具有小电路区域的软件无线电处理。解决方案：设备具有电路DRC，其具有可以高速改变配置并且可以动态地改变配置的结构，通用处理器和与诸如AD转换器的外部设备连接的接口，一个DA转换器。因此，通过使用软件无线电芯片来实现软件无线电，其中多个处理如发送，接收，同步和解调被时分地执行。因此，无线电信号处理中的不同处理可以分时地处理。因此，与用于通过将FPGA的区域分配到各个处理来执行处理的软件无线电系统相比，利用具有较小面积的电路来实现软件无线电。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005322266A Microprocessor of low power consumption and microprocessor system 有权
标题翻译：低功耗微处理器和微处理器系统的微处理器
公开(公告)号：JP2005322266A
公开(公告)日：2005-11-17
申请号：JP2005168976
申请日：2005-06-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMADA TETSUYA , HAYASHI TOMOICHI , NAKANO SADASHIGE , TSUNODA MASANOBU , NISHII OSAMU
IPC分类号： G06F9/38 , G06F1/04
摘要： PROBLEM TO BE SOLVED: To reduce useless power consumption of a floating-point arithmetic unit contained in a microprocessor. SOLUTION: In an instruction sequence supplied from an instruction cache 108, an instruction invalidating circuit 109 replaces an instruction not using the floating-point arithmetic unit with an invalid instruction, then the invalid instruction is held by a floating-point instruction register 111 and supplied to a floating-point decoder 119 in the floating-point arithmetic unit. If the invalid instructions are continued, the power consumption of the decoder 119 and a floating-point register 121 as well as a floating point data path 123 can be reduced. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：减少微处理器中包含的浮点算术单元的无用功耗。解决方案：在从指令高速缓存108提供的指令序列中，指令无效电路109用无效指令替换不使用浮点运算单元的指令，然后由浮点指令寄存器 111并提供给浮点运算单元中的浮点解码器119。如果继续无效指令，则可以减少解码器119和浮点寄存器121以及浮点数据路径123的功耗。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2010109110A Circuit board 审中-公开
标题翻译：电路板
公开(公告)号：JP2010109110A
公开(公告)日：2010-05-13
申请号：JP2008279061
申请日：2008-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TERADA KOICHI , TSUNODA MASANOBU , KASAI SHIGEHIKO
IPC分类号： H05K1/18 , G02F1/1345 , H05K3/32
摘要： PROBLEM TO BE SOLVED: To suppress a remaining distortion by heat causing a remaining unevenness of a display of a finished product when directly mounting a liquid crystal driver LSI (Large-Scale Integration) to a glass substrate with the use of the ACF (Anisotropic Conductive Film) or the like.
SOLUTION: A semiconductor component has a first coefficient of thermal expansion and a first inductive coupling part for giving and receiving signals to and from the other semiconductor component. A printed circuit board has a second coefficient of thermal expansion different from that of the semiconductor, and includes a second inductive coupling part for giving and receiving signals with the first inductive coupling part. A circuit board fixes the semiconductor component to the printed circuit board with the first inductive coupling part and the second inductive coupling part placed opposite, and signals are given and received among the semiconductor components.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过使用ACF直接将液晶驱动器LSI（大规模集成）安装到玻璃基板上时，通过热量抑制剩余的失真导致成品显示的不均匀性（各向异性导电膜）等。解决方案：半导体部件具有第一热膨胀系数和第一电感耦合部分，用于向和从另一个半导体部件发送和接收信号。印刷电路板具有与半导体不同的第二热膨胀系数，并且包括用于给予和接收与第一电感耦合部分的信号的第二感应耦合部分。电路板将半导体部件固定到印刷电路板上，其中第一电感耦合部分和第二电感耦合部件相对放置，并且在半导体部件之间给予和接收信号。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2010108204A Multichip processor 审中-公开
标题翻译：多媒体处理器
公开(公告)号：JP2010108204A
公开(公告)日：2010-05-13
申请号：JP2008279059
申请日：2008-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TSUNODA MASANOBU , CHIHARA NOBUHIRO
IPC分类号： G06F15/78 , G06F15/173 , H01L23/00 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： G06F15/8007 , G06F15/7896 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To achieve a low cost multi-processor for integration which is characterized by a reconfigurable inter-processor core connection topology for increasing scalable arithmetic performance and the degree of freedom by making variable the number of processor cores.
SOLUTION: In a multi-processor configured by laminating a plurality of unit chips having at least a processor core and a memory, the unit chip includes: a plurality of processor cores; a plurality of memories; a configuration control part for setting a connection relation between the processor cores and the memories and the outside of the chips; and a chip connection part for transmitting transaction between the processors or the memories or the configuration control part and the other unit chips to be carried out laminate connection, and the chip connection part is arranged rotationally symmetrically to the side sections of the unit chips, and any unit chip of the unit chips configured to be laminated is rotationally connected.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：实现用于集成的低成本多处理器，其特征在于可重构的处理器间核心连接拓扑，用于通过使可变的处理器核心数量来增加可扩展的算术性能和自由度。解决方案：在通过层叠具有至少处理器核心和存储器的多个单元芯片构成的多处理器中，单元芯片包括：多个处理器核心; 多个存储器; 用于设置处理器核与存储器之间的连接关系和芯片外部的配置控制部分; 以及用于在处理器或存储器之间传送交易的芯片连接部分或者要执行层叠连接的配置控制部分和其他单元芯片，并且芯片连接部分被布置成与单元芯片的侧部部分旋转对称，并且配置为层压的单元芯片的任何单元芯片被旋转地连接。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2007026560A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007026560A
公开(公告)日：2007-02-01
申请号：JP2005208027
申请日：2005-07-19
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： HANZAWA SATORU , WATANABE TAKASHI , TSUNODA MASANOBU , KONDO TAKEKI
IPC分类号： G11C15/04
CPC分类号： G11C15/04 , G11C15/043
摘要： PROBLEM TO BE SOLVED: To realize the availability improvement and the functionality expansion of a semiconductor device including a CAM (contents addressable memory). SOLUTION: A plurality of banks are provided, and the banks are provided with a CAM cell array and a latency control circuit. The respective bank are arranged in manners that bit lengths of storable entries are respectively determined to be different values and that row addresses are allocated to the entries in order of bit lengths. Further, the latency control circuit does not depend upon the banks, and has the same number of D flip-flops for each entry. The CAM performs a retrieving operation of entries with various bit lengths and simultaneously output coincidence signals. In addition, the CAM outputs a coincidence signal corresponding to an entry with high similarity among a plurality of coincidence signal preferentially. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：实现包括CAM（内容可寻址存储器）的半导体器件的可用性改进和功能扩展。解决方案：提供多个存储体，并且存储体设置有CAM单元阵列和等待时间控制电路。各存储体的排列方式是将可存储条目的位长度分别确定为不同的值，并且按照位长度的顺序将行地址分配给条目。此外，等待时间控制电路不依赖于存储体，并且对于每个条目具有相同数量的D触发器。 CAM执行具有各种位长度的条目的检索操作，同时输出重合信号。此外，CAM优先输出与多个符合信号中的高相似度的条目相对应的一致信号。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2006109025A The semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2006109025A
公开(公告)日：2006-04-20
申请号：JP2004292056
申请日：2004-10-05
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKADA MASASHI , TSUNODA MASANOBU , TANAKA HIROSHI , MOTOMURA TETSURO
IPC分类号： H03K19/173
CPC分类号： G06F9/3879 , G06F15/7867
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit with an access mechanism capable of realizing miniaturization of a hardware scale and improvement of usability regarding data access to a built-in memory and a peripheral circuit from an ALU cell arranged in an array shape. SOLUTION: The semiconductor integrated circuit is composed of a plurality of exclusive cell groups 1304, 1306, which execute memory access processing to the built-in memories 1313, 1312, corresponding to a plurality of the ALU cells. The exclusive cell groups 1304, 1306 are composed so that the access standardized with the built-in memory can be executed to the peripheral circuit 1201 and an LSI external device 206. In such a manner, the exclusive cell group is composed which executes the memory access processing to the built-in memory. Consequently, the ALU cell does not require the memory access mechanism. The reduction of an area and the improvement of use efficiency can be realized. Further, the improvement of the usability can be realized since it is possible to execute the standardized access to the built-in memory and the peripheral circuit or the like. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供具有能够实现硬件规模的小型化的访问机构的半导体集成电路以及关于从布置在其中的ALU单元对内置存储器和外围电路的数据访问的可用性的提高阵列形状。解决方案：半导体集成电路由对应于多个ALU单元的内置存储器1313,1312执行存储器访问处理的多个专用单元组1304,1306组成。专用单元组1304,1306被构成为能够对周边电路1201和LSI外部装置206执行利用内置存储器标准化的访问。以这种方式，组成执行存储器的排他单元组访问处理到内置内存。因此，ALU单元不需要存储器访问机构。可以实现面积的缩小和使用效率的提高。此外，可以实现可用性的提高，因为可以执行对内置存储器和外围电路等的标准化访问。版权所有（C）2006，JPO＆NCIPI

10. 发明专利

JP2010109113A Multilayer integrated circuit and production method of the same 审中-公开
标题翻译：多层集成电路及其生产方法
公开(公告)号：JP2010109113A
公开(公告)日：2010-05-13
申请号：JP2008279067
申请日：2008-10-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： CHIHARA NOBUHIRO , HOSOKI KOJI , TSUNODA MASANOBU
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a high-accuracy alignment method, in response to miniaturization of an integrated circuit, in a multiplayer integrated circuit that enables substrate-to-substrate communication that uses a dielectric coupling method.
SOLUTION: A DC current is passed through a communication coil 210 from a control circuit 200, the communication coil 210 formed on two or more integrated circuit substrates 30, thereby turning the communication coil 210 itself into an electrical magnet and carrying out high-accuracy alignment by the magnetic attracting force and repulsive force between the mutually two communication coils.
COPYRIGHT: (C)2010,JPO&INPIT

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