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1. 发明专利

DE3176548D1 DATA-PROCESSING SYSTEM WITH MAIN AND BUFFER STORAGE CONTROL 未知
公开(公告)号：DE3176548D1
公开(公告)日：1988-01-07
申请号：DE3176548
申请日：1981-12-15
申请人： HITACHI LTD
发明人： WAKAI KATSURO
IPC分类号： G06F9/38 , G06F12/08 , G06F13/18 , G06F13/28 , G06F13/16

2. 发明专利

DE3485737D1 未知
公开(公告)号：DE3485737D1
公开(公告)日：1992-06-25
申请号：DE3485737
申请日：1984-11-14
申请人： HITACHI LTD
发明人： KUBO KANJI , WAKAI KATSURO
IPC分类号： G06F12/10 , G06F12/14
摘要： @ An access control system for controlling the access to a storage which is divided into a hardware area inaccessible to ordinary programs and a software area for storing the ordinary programs, includes address registration means (20, 22) and access control means (23). The address registration means has a plurality of entries, each of which holds a previously-used address of the storage and a flag for indicating whether the previously-used address is included in the hardware area or not. Further, the address registration means indicates whether an address at which the storage is to be accessed, is present in the address registration means or not. The access control means controls the access to the storage in accordance with the flag from the address registration means, a signal indicative of whether the to-be-accessed address of the storage is present in the address registration means or not, and the access mode which is now used.

3. 发明专利

DE2942998A1 未知
公开(公告)号：DE2942998A1
公开(公告)日：1980-08-14
申请号：DE2942998
申请日：1979-10-24
申请人： HITACHI LTD
发明人： ISHIKAWA SAKOU , WATANABE YUTAKA , WAKAI KATSURO
IPC分类号： G06F11/10 , G06F11/14 , G06F12/16 , G11C29/00 , G06F11/12
摘要： In a system which employs SEC-DED codes constituted by data bits added to redundant bits and is capable of detecting and correcting a single bit error while detecting a double or more bit error, detection is made on miscorrection ascribable to a triple bit error. When a single bit error is detected by an error detecting and correcting circuit in the SEC-DED code read out from a memory, all the corrected data bits are inverted in state and rewritten in the memory after having been added to new redundant bits. Subsequently, the data bits together with the redundant bits are read out from the memory and supplied to the error detecting and correcting circuit. The data bits obtained from the error detecting and correcting circuit are compared with the corrected and inverted data bits available before being written in the memory, to thereby determine the presence of an error encompassing more than (m+1) bits on the basis of the result of comparison.

4. 发明专利

DE3585401D1 未知
公开(公告)号：DE3585401D1
公开(公告)日：1992-03-26
申请号：DE3585401
申请日：1985-11-19
申请人： HITACHI LTD
发明人： WAKAI KATSURO
IPC分类号： G06F11/22 , G01R31/3185 , G06F11/26
摘要： A scan control apparatus performs data scan-in operation to data storage elements (30, 40) each constituting a bit of data unit. Data of the plural data storage elements (30, 40) designated by scan address are read out into a register (12) where the data at the bit position designated by the scan address is replaced by data to be scanned-in. Subsequently, the plurality of the data storage elements are reset simultaneously to thereby set the data in the register to the original data storage elements.

5. 发明专利

JPH0457031B2 失效
公开(公告)号：JPH0457031B2
公开(公告)日：1992-09-10
申请号：JP2144883
申请日：1983-02-14
申请人： HITACHI LTD
发明人： MYOSHI MASAYUKI , WAKAI KATSURO , ONIZUKA NOBUHIKO , KATO ZENTARO
IPC分类号： G06F11/25 , G06F17/50 , G06F19/00

6. 发明专利

JPS61123939A Scan system of information processor 失效
标题翻译：信息处理器扫描系统
公开(公告)号：JPS61123939A
公开(公告)日：1986-06-11
申请号：JP24441984
申请日：1984-11-21
申请人： Hitachi Ltd
发明人： WAKAI KATSURO
IPC分类号： G06F11/22 , G01R31/3185
CPC分类号： G01R31/318555 , G01R31/318558
摘要： PURPOSE: To decrease greatly the number of logical gates of scan-in by reading out the contents of a data memory element, and setting data to be set to a one bit data memory element to which the data is to be scanned in.
CONSTITUTION: In case of the scan-in, data of a one bit information unit, including FFs 401-0W401-7 which are scan-in objects to be indicated by a physical scan-in address, is once scanned out. One bit scan data is merged to it, and the FFs 401-0W401-7 of this information unit are set all together, and then the data equivalent to the information unit are scanned in. Only one bit changes as a result, and the purpose can be attained by scan logics of two gates per FF, namely, AND gates 404 and 405. Accordingly, tens of thousands of logical gates can be reduced in the information processors as a whole.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过读出数据存储器元件的内容，大大减少扫描逻辑门的数量，并将要设置的数据设置为要扫描数据的一位数据存储元件。构成：在扫描的情况下，一旦扫描出包括作为要由物理扫描地址指示的扫描对象的FF 401-0-401-7的一位信息单元的数据。将一位扫描数据合并到该信息单元的FF401-0-401-7中，然后扫描与信息单元相当的数据，结果只有一位改变，可以通过每个FF的两个门的扫描逻辑，即与门404和405来实现目的。因此，在整个信息处理器中可以减少数万个逻辑门。

7. 发明专利

JPS6113613B2 JPS6113613B2 - 失效
公开(公告)号：JPS6113613B2
公开(公告)日：1986-04-14
申请号：JP8511880
申请日：1980-06-25
申请人： Hitachi Ltd
发明人： HAYASHI KENJI , MYADERA HIROO , WAKAI KATSURO
IPC分类号： G06F9/22 , G06F11/22 , G06F11/28
CPC分类号： G06F11/22

8. 发明专利

JPS51103740A 失效
公开(公告)号：JPS51103740A
公开(公告)日：1976-09-13
申请号：JP2850175
申请日：1975-03-08
申请人： HITACHI LTD
发明人： WAKAI KATSURO
IPC分类号： G06F13/12 , G06F3/00 , G06F5/00 , G06F13/00

9. 发明专利

JP2509524B2 失效
公开(公告)号：JP2509524B2
公开(公告)日：1996-06-19
申请号：JP23135093
申请日：1993-09-17
申请人： HITACHI LTD
发明人： NAKAMURA KOJI , KUBO KANJI , WAKAI KATSURO , KISHI MAKOTO , MATSUO TOSHIHISA
IPC分类号： G06F12/00

10. 发明专利

JPH01116848A BUFFER MEMORY 失效
公开(公告)号：JPH01116848A
公开(公告)日：1989-05-09
申请号：JP27693387
申请日：1987-10-30
申请人： HITACHI LTD
发明人： KUBO KANJI , WAKAI KATSURO
IPC分类号： G06F12/08
摘要： PURPOSE:To improve the throughput of a processor by using only a fixed block position of a specific block to operate the processor with respect to data which is less probably used again. CONSTITUTION:A buffer memory 6 consisting of plural blocks including the specific block and a means which determines the use of only the specific block in the buffer memory 6 or the use of another arbitrary block in accordance with designated contents of an access request source are provided; and for example, only the specific block is used for read of the operand of an instruction MVCL (move character long). Since block transfer generated in accordance with this read of the operand of the instruction MVCL is registered in the fixed position of the specific block, the instruction MVCL is executed without driving out the other data stored on the buffer memory 6, and the use rate of the buffer memory is improved.

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