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    • 2. 发明专利
    • HEAT-TREATING EQUIPMENT
    • JPH01256119A
    • 1989-10-12
    • JP8438988
    • 1988-04-06
    • HITACHI LTDNIPPON TOKYO ELECTRON KK
    • TOCHIKUBO HIROOTATEFURU NOBORUINABA KEIZOMASUYAMA SHIGEJIHAYAKAWA JUNICHI
    • H01L21/22
    • PURPOSE:To increase throughput, and prevent the generation of thermal stress dislocation, by containing, in an inner cylinder, a jig retaining a plurality of objects to be treated, constituting them so as to be carried in a processing chamber and carried out therefrom in a state where the almost whole part is enclosed, and providing the hollow part of the inner cylinder with a gas supplying channel to compulsorily circulate the gas. CONSTITUTION:A wafer group 6 and a boat 7 retaining it are carried into a process tube 1 and carried out therefrom, in the state where they are enclosed by an inner cylinder 12. When objects 6 to be treated are carried in a processing chamber 6 and carried out therefrom, the inner cylinder 12 covering the the objects 6 to be treated and a jig 7 for the objects to be treated is firstly heated and cooled by radiating heat from the processing chamber. After the inner cylinder 12 is wholly and uniformly heated, the objects 6 to be treated are heated and colled. As a result, the temperature distribution difference in the objects to be treated becomes small, so that thermal stress dislocation defect failures and the deformation of the objects 6 to be processed are restrained.
    • 5. 发明专利
    • MANUFACTURE OF COMPOUND SEMICONDUCTOR DEVICE
    • JPS62122276A
    • 1987-06-03
    • JP26112885
    • 1985-11-22
    • HITACHI LTD
    • INABA KEIZOTOCHIKUBO HIROOSHIMIZU SHUICHIKANAI AKIRA
    • H01L21/205H01L21/338H01L29/80H01L29/812
    • PURPOSE:To obtain the manufacturing method of a GaAs FFT characterized by no dispersion in threshold voltage VTH and source-drain current IDSS, by forming an active layer having a required thickness on a substrate, and partially forming a high-concentration semiconductor layer, which is ohmic-contacted with source and drain electrodes, on the active layer by a selective epitaxial method. CONSTITUTION:On one main surface of a GaAs substrate 1, a gate electrode G comprising metal, which forms a Schottky barrier, and source and drain electrodes comprising metal, which is ohmic-contacted with the substrate so as to hold the gate in-between, are formed. In this manufacturing method of GaAs FET, an n-type active layer 3 having a required thickness is formed on the GaAs substrate 1. A high-concentration n type layer 9, which is ohmic- contacted with the source and drain electrodes, is partially formed on the active layer by a selective epitaxial method. Thus the gate electrode G is formed on the n-type active layer 3, which has a substantially recessed shape. Thus the width of the active layer directly beneath the gate can be controlled, and dispersion in VTH and the like can be reduced.
    • 6. 发明专利
    • MANUFACTURE OF SEMICONDUCTOR DEVICE
    • JPS5878438A
    • 1983-05-12
    • JP18131282
    • 1982-10-18
    • HITACHI LTD
    • NOMURA MASATAKANISHIDA SUMIOTOCHIKUBO HIROO
    • H01L21/205H01L21/762H01L27/12
    • PURPOSE:To remove the stress of a polycrystal silicon layer requiring thickness, through which handling is facilitated, and to prevent the warpage of a base body by positioning an insulating film made of SiO2 into the polycrystal silicon layer. CONSTITUTION:An N type vapor growth layer 32 is formed to the main surface of an N type single crystal silicon substrate 31 having low resistance through a vapor growth method, and a film 33 made of a selectively oxidizable substance is shaped to one part of the surface of the N type vapor growth layer 32. Isolation layers 34 made of SiO2 are formed through oxidation treatment as using the film 33 as a mask while an N type silicon region 32a isolated by the isolation layers 34 is shaped. The film 33 is removed through etching, and an oxide film 35 made of SiO2 is molded to the whole surface of the main surface of the semiconductor substrate containing the N type vapor growth layer 32 exposed and the isolation layer 34. The polycrystal silicon layer 36a is formed to the whole surface of the oxide film 35, and an insulating film 37a made of SiO2 and further the polycrystal silicon layer 36b, an insulating film 37b made of SiO2 and the polycrystal silicon layer 36c are alternately stacked and shaped onto the polycrystal silicon layer 36a. The whole is removed in parallel through mechanical polishing and chemical etching processing.