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1. 发明专利

JPS53143143A VARYING METHOD FOR AUTOMATIC PROGRAM 失效
公开(公告)号：JPS53143143A
公开(公告)日：1978-12-13
申请号：JP5759177
申请日：1977-05-20
申请人： HITACHI LTD
发明人： KITADA TAKAYOSHI , IWASA YUUZABUROU
IPC分类号： G06F9/02
摘要： PURPOSE:To make unnecessary programming units such as an operator console, by realizing a program suitable for the corresponded control loop, through the alteration of wirings of external terminals of a computer with external connectors removable to external terminals.

2. 发明专利

JPS5745653A Multiplex output collation system 失效
标题翻译：多输出输出系统
公开(公告)号：JPS5745653A
公开(公告)日：1982-03-15
申请号：JP12108280
申请日：1980-09-03
申请人： Hitachi Ltd
发明人： YAMAOKA HIROMASA , IWASA YUUZABUROU
IPC分类号： G06F11/18 , G06F11/16 , G06F13/00 , G06F15/16 , G06F15/177
CPC分类号： G06F11/167
摘要： PURPOSE:To process the collation of multipoint data with one data collation set, by making collation through the readout of the content of registers which are accessible, and transmitting the coincidence data as the address for the counter value to the output device. CONSTITUTION:Data outputted from each duplex CPU(not shown) via buses 101, 102 are inputted to registers 51, 52. The write-in address of the data section is designated with the address of the buses 101, 102 and the readout address of data is designated with the value of a counter 53. The data of the registers 51, 52 designated with the counter 53 is collated 54, and only when they coincide, the data is outputted to a bus 103 by taking the value of the counter 53 as the address section. If uncoincidence of data has been observed for longer than a prescribed time, an error signal is transmitted.
摘要翻译：目的：通过对可访问的寄存器的内容的读出进行排序，并将符合数据作为计数器值的地址发送到输出设备，来处理多点数据与一个数据对照集的对照。构成：经由总线101,102从每个双工CPU（未示出）输出的数据被输入到寄存器51,52。数据部分的写入地址由总线101,102的地址和用计数器53的值指定数据。用计数器53指定的寄存器51,52的数据被对照54，并且只有当它们一致时，通过取计数器53的值将数据输出到总线103 作为地址部分。如果观察到数据的长度超过规定时间，则发送错误信号。

3. 发明专利

JPS5433638A TRANSMISSION BUS SEPARATION SYSTEM 失效
公开(公告)号：JPS5433638A
公开(公告)日：1979-03-12
申请号：JP9956477
申请日：1977-08-22
申请人： HITACHI LTD
发明人： IWASA YUUZABUROU , TACHIKAWA MAKOTO
IPC分类号： H04B3/46 , G06F3/00 , G06F11/00 , G06F11/18 , G06F11/22 , G06F13/00 , H04L12/40
摘要： PURPOSE:To realize the delivery system of high reliability in which the unit is always operated to fail safe side, by enabling the separation of the transmission bus at failed data delivery and the self-diagnosis, through the provision of the watchdog timer and the relay.

4. 发明专利

JPS5313744A SPEED STANDARD COMMAND GENERATOR FOR ELEVATOR 失效
公开(公告)号：JPS5313744A
公开(公告)日：1978-02-07
申请号：JP8839276
申请日：1976-07-24
申请人： HITACHI LTD
发明人： OOHIRA TAKESHI , HONJIYOU SENHIKO , KAMEYAMA SHIROU , IWASA YUUZABUROU
IPC分类号： B66B1/24 , B66B1/28 , B66B1/30 , B66B1/36 , B66B1/50 , B66B3/00 , H02P29/00
摘要： PURPOSE:To provide a speed standard command generator for an elevator, which can freely set the decelerated distance without providing a plurality of position detectors such as proximity switches.

5. 发明专利

JPS60132441A DATA TRANSMISSION METHOD 失效
公开(公告)号：JPS60132441A
公开(公告)日：1985-07-15
申请号：JP24155483
申请日：1983-12-21
申请人： HITACHI LTD
发明人： YAMAMOTO TOSHIFUMI , IWASA YUUZABUROU
IPC分类号： H04L12/42
摘要： PURPOSE:To improve the reliability of a data transmission system by rewriting and transferring the reception confirming signal by each station that received data in the data transmission direction of a transmission network. CONSTITUTION:A station ST3 which copies first a frame rewrites the contents of a frame status FS to FS1 from FS0 and delivers it after copying the data. In the same way, the station which copied the frame rewrites and delivers the contents of the FS when sending the frame to the next station. The contents of the FS of a frame returned to a transmission state ST1 after having a circulation along a ring are equal to an FSP obtained through successive writing. Thus the station ST1 can confirm that all addressed P units of stations have copied frames respectively.

6. 发明专利

JPS6045801A MULTIPLEXED CONSTITUTION CONTROLLER 失效
公开(公告)号：JPS6045801A
公开(公告)日：1985-03-12
申请号：JP15320683
申请日：1983-08-24
申请人： HITACHI LTD
发明人： HIROKI TAKESHI , IWASA YUUZABUROU , YANAGIDA SADAO
IPC分类号： G05B9/03 , G06F11/18
摘要： PURPOSE:To avoid the data discordance, etc. due to the asynchronous processing by providing a transmisson timing control circuit at the transmission side to start transmission of data all at once and having collation of data at the reception side when the reception is through with a series of data. CONSTITUTION:A transmission timing control circuit set at the transmission side starts data transmission of own station at a time point when the transmission start signals of own station as well as other two stations which are sent via a timing detection line are all active. Then data transmitters start data transmission all at once. The signals sent from triplex processors are applied to frame processing circuits 404-406 via a data transmission circuit 400. Then data are extracted out of signal frames and stored successively to reception data buffers 410-412. The circuits 404-406 activate reception end signal 413-415 when detecting a close flag of the signal frame. When signals 413-415 are all active, the contents of buffers 410-412 are supplied to a multiplexed signal processing circuit 418 and then transferred to an input/output device after collation.

7. 发明专利

JPS6031645A CENTRAL PROCESSING UNIT 失效
公开(公告)号：JPS6031645A
公开(公告)日：1985-02-18
申请号：JP13944583
申请日：1983-08-01
申请人： HITACHI LTD
发明人： YAMAOKA HIROMASA , OKAMOTO TADASHI , IWASA YUUZABUROU , KIMURA KOUICHI
IPC分类号： G06F9/32 , G05B19/05 , G06F9/30
摘要： PURPOSE:To execute a ladder sequence operation directly in parallel by providing a function executing inter-bit operation to an operation part of a processor to be used for an industrial plant or the like. CONSTITUTION:A program counter 13 applies an address 201 to a program memory 21 and is counted up by +1 every operation step. The memory 12 stores the information of a ladder sequence to be executed as a program. An input inversion part 111 inverts bits ''1'' corresponding to outputs P2-P5 of the memory 12 logically out of input data 225. A logical operator 117 finds out AND between the output 220 of the inversion part 111 and the contents 223 of an accumulator. An inter-bit operator 113 finds out OR between corresponding adjacent bits when the outputs P6-P8 of the program memory 12 are ''1'' and its output 222 is latched by the accumulator 114 together with a clock pulse 206. When the instruction is an output instruction, the contents 223 of the accumulator 114 are outputted to a data bus 102 through an output gate 115.

8. 发明专利

JPS56147227A DEVICE FOR READING DATA FROM PLURAL SETTERS 失效
公开(公告)号：JPS56147227A
公开(公告)日：1981-11-16
申请号：JP5044680
申请日：1980-04-18
申请人： HITACHI LTD
发明人： IWASA YUUZABUROU
IPC分类号： G06F3/023 , G06F3/02
摘要： PURPOSE:To simplify the structure of the interface part, by reading input data from plural setters to the processor through the common interface circuit. CONSTITUTION:When SW1 of push-button switch 3031 of setter 31 is depressed, interruption signal INT1 is sent to the interrution signal receiving circuit of processor 4. Processor 4 recognizes thi interruption signal INT1 and sends selection signal SEL1 from the setter selection signal generating circuit to switching transistor 3041 to form the setting circuit. Consequently, input data is coded and is taken into the processor through data bus 402 by the operation of SW1 of push-button switch 3031. If push-button switches of plural setters are operated simultaneously, processor 4 generates setter selection signals SEL1-SELN in accordance with the order of arrival or priority of interruption signals INT1-INTN, and input data are taken into the processor successively in time division.

9. 发明专利

JPS60218934A RADIATION LINEAR PULSE TRANSMITTER 失效
公开(公告)号：JPS60218934A
公开(公告)日：1985-11-01
申请号：JP7506984
申请日：1984-04-16
申请人： HITACHI LTD
发明人： ISHII KAZUHIKO , YAMAMOTO TOSHIFUMI , KAIHARA AKIHISA , IWASA YUUZABUROU
IPC分类号： H04B10/556 , G01T1/17 , G01T1/20 , H04B10/00 , H04B10/07 , H04B10/2507 , H04B10/90 , H04B15/00 , H04L25/06
摘要： PURPOSE:To compensate the change of an analog level due to the variation of characteristics of an optical fiber cable, etc., and to measure exactly linear pulse by superposing a DC signal onto a signal transmitted via an optical transmission system and setting the threshold value of a received signal at the reception side with the voltage proportional to the level of said superposed signal. CONSTITUTION:An addition signal (S1+S2) of a radiation linear pulse signal S1 to be measured and a DC component signal S2 is supplied to an attenuator 61. The output X2 of the attenuator 61 is shown by an equation I , where the attenuation factor is referred to as alpha. A discriminator 62 isolates a DC component aS2 and a linear pulse component aS1 out of the signal X2 as shown by equations II and III. A threshold value control circuit 63 has the set value beta for correction of various types of noise components, and an equation IV shows the relation between an input X4 and an output V1. A comparator 64 obtains a ratio between X3 and V1 to satisfy X5=X3/V1=S1/betaS2 for an output X5. Thus the output X5 contains no component (a). In other words, the output X5 of the comparator 64 is not affected an attenuation factor (a) obtained by the characteristic variation.

10. 发明专利

JPS60186936A PROGRAMMABLE CONTROLLER 失效
公开(公告)号：JPS60186936A
公开(公告)日：1985-09-24
申请号：JP4259284
申请日：1984-03-05
申请人： HITACHI LTD
发明人： YAMAOKA HIROMASA , OKAMOTO TADASHI , SHIMOYAMA KAZUHIKO , TAKAKURA MITSUO , KURISU YOFUMI , IWASA YUUZABUROU
IPC分类号： G06F9/38 , G05B19/04 , G05B19/05 , G06F9/34
摘要： PURPOSE:To increase the processing speed of a programmable controller by separating the arithmetic part of an operand address from an execution arithmetic part of instruction and reading an instruction and an operand in parallel to each other. CONSTITUTION:A programmable controller consists of a CPU1, a program memory 12 and an I/O13. The CPU1 reads out a memory instruction through a program counter 4 and stores it temporarily to an instruction register 11. The contents of the register 11 are added by an adder 29, and an operand which uses the added value as an address is read out and stored temporarily to an I/O read data register 26. Then an instruction is transferred to an instruction register 18, and an arithmetic circuit 7 calculates the contents of the register 26 and an accumulator 10. In this case, three blocks, i.e., the counter 4 and the memory 12, the register 11 and the adder 29, the I/O13 and the circuit 7 and the register 26 and the accumulator 10 can work in parallel to each other.

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