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1. 发明专利

JP2003287499A Emission spectroscopic processing apparatus and method for plasma processing 有权
标题翻译：排放光谱处理装置和等离子体处理方法
公开(公告)号：JP2003287499A
公开(公告)日：2003-10-10
申请号：JP2003049354
申请日：2003-02-26
申请人： Hitachi High-Technologies Corp , Hitachi Kasado Eng Co Ltd , Hitachi Ltd , 日立笠戸エンジニアリング株式会社 , 株式会社日立ハイテクノロジーズ , 株式会社日立製作所
发明人： USUI TAKETO , KAJI TETSUNORI , KIMURA SHIZUAKI , FUJII TAKASHI
IPC分类号： G01N21/71 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To sense an infinitesimal change of a fast spectral separation with good reproducibility in a plasma processing unit or the like.
SOLUTION: An emission spectroscopic processing apparatus comprises a spectroscope 3 for spectrally separating an input light from a plasma processing unit, a photodetector 4 having a series of photodetecting elements each for detecting an amount of the separated input light at each wavelength, a first signal holding unit 10 for sequentially holding detection signals of partial light receiving elements adjacent in the series of the elements in first period, an adder 11 for adding the detection signals of the adjacent elements of the photodetector including the detection signal of the held partial adjacent element, and a second signal holding unit 12 for sequentially holding the added output of the adder, and further a signal processing unit 9 for deciding a state of the processing unit based on an output of the second holding unit.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：在等离子体处理单元等中以良好的再现性感测快速光谱分离的无限小变化。解决方案：发射光谱处理装置包括用于光谱分离来自等离子体处理单元的输入光的分光镜3，具有一系列用于检测每个波长的分离的输入光量的光检测元件的光电检测器4，第一信号保持单元10，用于在第一周期中顺序地保持在该系列元件中相邻的部分光接收元件的检测信号;加法器11，用于将包括所保持的部分相邻的检测信号的光检测器的相邻元件的检测信号相加以及用于顺序保持加法器的相加输出的第二信号保持单元12，以及用于基于第二保持单元的输出来判定处理单元的状态的信号处理单元9。版权所有（C）2004，JPO

2. 发明专利

JP2006119145A Method and device for processing semiconductor wafer 审中-公开
标题翻译：用于处理半导体波形的方法和装置
公开(公告)号：JP2006119145A
公开(公告)日：2006-05-11
申请号：JP2005328237
申请日：2005-11-14
申请人： Hitachi High-Technologies Corp , Hitachi Kasado Eng Co Ltd , Hitachi Ltd , 日立笠戸エンジニアリング株式会社 , 株式会社日立ハイテクノロジーズ , 株式会社日立製作所
发明人： USUI TAKETO , FUJII TAKASHI , KIKKAI MOTOHIKO , KAJI TETSUNORI
IPC分类号： G01B11/06 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To provide a method for processing a material to be processed capable of precisely measuring an actual thickness of the material in a plasma process, especially a plasma etching process, and a device therefor.
SOLUTION: The method for processing a semiconductor wafer processes the surface film of the semiconductor wafer arranged in a vacuum processing chamber by using plasma formed in the vacuum processing chamber. It comprises a step of receiving a plurality of wavelengths of interference beams obtained from the surface of the semiconductor wafer during the processing so as to detect derivative values of strength of the interference beams for a plurality of the respective wavelengths; a step of determining a range of the film thickness for an interference beam with a first wavelength from among the detected interference beams of a plurality of the wavelengths by using a pattern in which the derivative value of the strength thereof passes through a zero point; and a step of judging the film thickness from the range of the film thickness for an interference beam with a second wavelength from among the interference beams of a plurality of the wavelengths by using a pattern in which the derivative value of the strength thereof passes through a zero point.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于处理能够在等离子体工艺，特别是等离子体蚀刻工艺中精确测量材料的实际厚度的材料的处理方法及其装置。解决方案：用于处理半导体晶片的方法通过使用在真空处理室中形成的等离子体处理布置在真空处理室中的半导体晶片的表面膜。它包括在处理期间接收从半导体晶片的表面获得的多个波长的干涉光束的步骤，以便检测多个相应波长的干涉光束的强度的导数值; 通过使用其强度的导数值通过零点的图案，从多个波长的检测干涉光束中确定具有第一波长的干涉光束的膜厚的范围的步骤; 以及通过使用其强度的导数值通过一个波长的图案，从多个波长的干涉光束之中的第二波长的干涉光束的膜厚度的范围来判断膜厚度的步骤零点版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005217448A Emission spectroscopic process apparatus and method for plasma process 有权
标题翻译：发射光谱过程装置和等离子体处理方法
公开(公告)号：JP2005217448A
公开(公告)日：2005-08-11
申请号：JP2005120109
申请日：2005-04-18
申请人： Hitachi High-Technologies Corp , Hitachi Kasado Eng Co Ltd , Hitachi Ltd , 日立笠戸エンジニアリング株式会社 , 株式会社日立ハイテクノロジーズ , 株式会社日立製作所
发明人： USUI TAKETO , KAJI TETSUNORI , KIMURA SHIZUAKI , FUJII TAKASHI
IPC分类号： H01L21/3065
摘要： PROBLEM TO BE SOLVED: To sense a quick infinitesimal change of a separated spectrum with good reproducibility in a plasma process unit or the like. SOLUTION: An emission spectroscopic process apparatus comprises a spectroscope 3 for spectrally separating an input light from the process unit, a photodetector 4 having a series of photodetecting elements each for detecting an amount of the separated input light at each wavelength, a first signal holding unit 10 for sequentially holding detecting signals of partial photodetecting elements adjacent in the series of photodetecting elements in a first period, an adder 11 for adding the detecting signals of the adjacent photodetecting elements of the photodetector including the detecting signals held by the adjacent partial photodetecting elements, and a second signal holding unit 12 for sequentially holding the added output of the adder, and further a signal process unit 9 for deciding a state of the process unit from an output of the second signal holding unit. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在等离子体处理单元等中以良好的再现性感测分离光谱的快速无限小变化。解决方案：一种发射分光处理装置，包括用于光谱分离来自处理单元的输入光的分光镜3，具有一系列光检测元件的光电检测器4，每个光检测元件用于检测每个波长处的分离的输入光的量;第一信号保持单元10，用于在第一周期中顺序地保持在一系列光电检测元件中相邻的部分光电检测元件的检测信号;加法器11，用于将包括由相邻部分保持的检测信号的光检测器的相邻光检测元件的检测信号相加; 光检测元件和用于顺序保持加法器的相加输出的第二信号保持单元12，以及用于根据第二信号保持单元的输出来判定处理单元的状态的信号处理单元9。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2003083720A Method and apparatus for measuring treatment amount of film in semiconductor-element manufacturing process, method and apparatus for treatment of material to be treated by using them as well as method and apparatus for deciding end point by using them 有权
标题翻译：用于测量半导体元件制造工艺中的膜的处理量的方法和装置，用于如何使用它们来处理待处理的材料的方法和装置以及使用它们来决定终点的装置
公开(公告)号：JP2003083720A
公开(公告)日：2003-03-19
申请号：JP2001280908
申请日：2001-09-17
申请人： Hitachi High-Technologies Corp , Hitachi Kasado Eng Co Ltd , Hitachi Ltd , 日立笠戸エンジニアリング株式会社 , 株式会社日立ハイテクノロジーズ , 株式会社日立製作所
发明人： USUI TAKETO , FUJII TAKASHI , KIKKAI MOTOHIKO , KAJI TETSUNORI , YAMAMOTO HIDEYUKI
IPC分类号： G01B11/06 , H01L21/302 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To measure the actual etching depth and the residual film amount of a layer to be treated precisely in an on-line manner and to decide the end point of a process.
SOLUTION: A standard pattern using a wavelength as a parameter for the differential value of interference light with reference to the prescribed step of a first material to be treated and a standard pattern using a wavelength as a parameter for the differential value of interference light with reference to the prescribed mask residual film thickness of the material to be treated are set. Then, the intensity of interference light regarding a second material to be treated whose constitution is identical to that of the first material to be treated is measured regarding a plurality of wavelengths, and an actual pattern using a wavelength as a parameter fro the differential value of the measured intensity of the interference light is found. On the basis of the standard pattern and on the basis of the actual pattern for the differential value, the step and the mask residual film thickness of the second material to be treated are found. The end point of the process is decided on the basis of the found step and the found mask residual film thickness of the second material to be treated.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：以在线方式精确地测量被处理层的实际蚀刻深度和残留膜量，并决定工艺的终点。解决方案：参考第一待处理材料的规定步骤，使用波长作为干涉光的差分值的参数的标准图案，以及使用波长作为参考的干涉光的差分值的参数的标准图案设定待处理材料的规定掩模残留膜厚度。然后，测定与多个波长相同的构成与第一待处理材料相同的被处理材料的干涉光的强度，使用波长作为参考的实际图案，发现干涉光的测量强度。基于标准图案，并且基于差分值的实际图案，找到待处理的第二材料的台阶和掩模残留膜厚度。基于所处理的第二材料的发现步骤和所找到的掩模残留膜厚来确定工艺的终点。

5. 发明专利

JP2005197761A Bay of semiconductor wafer production line, the semiconductor wafer production line, bay of liquid crystal production line and the liquid crystal production line 有权
标题翻译：半导体晶圆生产线，半导体波长生产线，液晶生产线和液晶生产线
公开(公告)号：JP2005197761A
公开(公告)日：2005-07-21
申请号：JP2005055903
申请日：2005-03-01
申请人： Hitachi High-Technologies Corp , Hitachi Kasado Eng Co Ltd , 日立笠戸エンジニアリング株式会社 , 株式会社日立ハイテクノロジーズ
发明人： UCHIMAKI YOICHI , EGAWA YUKO , KAJI TETSUNORI
IPC分类号： G02F1/13 , B65G49/06 , G05B19/418 , H01L21/677 , H01L21/68
CPC分类号： Y02P90/02
摘要： PROBLEM TO BE SOLVED: To provide a bay that can prevent rate control of wafer transport and wafer take up scrambling caused by wafer treatment differences between processors in the bay, and that can prevent lowering of throughput. SOLUTION: The bay 100 of the semiconductor production line is equipped with a single wafer transport line 120 which has a loop-like planar shape that transports semiconductor wafers W on a single piece basis, and is composed of: a transport line 121 having a nearly horizontal plane for semiconductor wafer transport that transports wafers on a single wafer basis; and another transport line 122 having a semiconductor wafer plane that counters the semiconductor wafer transport plane of the transport line 121 in the vertical direction. Inside the single-wafer transport line 120, there are provided a control system that controls the proper use of the transport line 121 or 122, based on semiconductor wafer treatment information, and transport devices 11 to 16 used for wafer delivery on a single wafer basis between the transport lines 121 and 122 and multiple processors 101 to 106, arranged side by side to perform predetermined treatment of semiconductor wafers. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供可以防止晶片传输的速率控制和晶片占用由间隔中的处理器之间的晶片处理差异引起的加扰并且可以防止吞吐量降低的间隔。解决方案：半导体生产线的隔间100配备有单个晶片输送线120，该晶片输送线120具有单片式输送半导体晶片W的环状平面形状，并且由以下部分组成：输送线121 具有用于在单个晶片基础上传输晶片的半导体晶片传输的接近水平面; 另一个输送线122具有在垂直方向上对输送线121的半导体晶片输送平面进行计数的半导体晶圆面。在单晶片传输线120内部，提供了一种控制系统，其基于半导体晶片处理信息控制传输线121或122的适当使用，以及用于在单个晶片基础上进行晶片传送的传输装置11至16 在传送线121和122之间以及多个处理器101至106并排布置以执行半导体晶片的预定处理。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2003282669A Method and device for transporting substrate 有权
标题翻译：用于运输基板的方法和装置
公开(公告)号：JP2003282669A
公开(公告)日：2003-10-03
申请号：JP2002086199
申请日：2002-03-26
申请人： Hitachi High-Technologies Corp , Hitachi Kasado Eng Co Ltd , 日立笠戸エンジニアリング株式会社 , 株式会社日立ハイテクノロジーズ
发明人： UCHIMAKI YOICHI , EGAWA YUKO , KAJI TETSUNORI
IPC分类号： B65G1/00 , B65G49/07 , H01L21/00 , H01L21/677 , H01L21/68
CPC分类号： H01L21/67727 , H01L21/67276 , H01L21/67736 , H01L21/67778 , Y10S414/135 , Y10S414/137 , Y10S414/141
摘要： PROBLEM TO BE SOLVED: To provide a method and a device for transporting single wafer in which transport for an wafer and connection for the wafer between a wafer transport means and each processing device are prevented from being rate- controlled, and throughput is prevented from deteriorated, even if processes differ from one another for each processing device in a bay. SOLUTION: Each of bays 100, 200, 300,... is connected to an inter-bay transport line 400 through each of bay stockers 130, 230, 330,..., respectively. The bay 100 consists of a loop-like sheet-fed transport line 120, and processing devices 101-106 that are placed side by side along a direction crossing a transport direction of the inter-bay transport line 400. The processing devices 101-103 are placed side by side on one side of the sheet-fed transport line 120. The processing devices 104-106 are placed side by side on the other side of the line. The processing devices 101-106 comprises transport robots 11-16 and a chamber (not shown in a figure) in which a wafer W is processed one by one. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种传输单晶片的方法和装置，其中防止晶片的传输和晶片在晶片传送装置和每个处理装置之间的连接被速率控制，并且吞吐量为即使处理间隔中的每个处理装置的处理彼此不同，也防止了劣化。解决方案：每个隔间100,200,300，...分别通过每个隔间储存器130,230,330，...连接到间隔间输送线400。海湾100由环状单张纸输送线120和沿着与间隔间输送线400的输送方向交叉的方向并排放置的处理装置101-106组成。处理装置101-103 被并排地放置在单张纸输送线路120的一侧。处理装置104-106并排放置在线的另一侧。处理装置101-106包括输送机器人11-16和其中晶片W逐个处理的室（未示出）。版权所有（C）2004，JPO

7. 发明专利

JP2005050856A Process treatment equipment and washing method thereof 审中-公开
标题翻译：工艺处理设备及其洗涤方法
公开(公告)号：JP2005050856A
公开(公告)日：2005-02-24
申请号：JP2003202970
申请日：2003-07-29
申请人： Hitachi Kasado Eng Co Ltd , 日立笠戸エンジニアリング株式会社
发明人： KUDO KATSUYOSHI , TSUSHIMA HIROSHI , MATSUMOTO TOKUYUKI , KAJI TETSUNORI
IPC分类号： C23C14/00 , C23C16/44 , H01L21/205 , H01L21/304 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To solve the problem that in process treatment equipment, sticking of the reaction product to a reaction chamber inner wall and internal structure object is not avoided, the cleaning work needing periodical cleaning usually uses pure water or IPA (isopropyl alcohol), etc. and in the system in which manual wet cleaning work in a state that inside of the equipment is opened to the air is the main, water content is left in the equipment by the influence of long time opening and wet cleaning, and a lot of time is necessary for removal and restoration of outgassing by evacuation to the state that influence to the next treatment until it effect does not exist. SOLUTION: A system is provided wherein dry ice is used for the cleaning medium, a jet mechanism of the dry ice is installed in the process treatment equipment, and cleaning is performed in the state that mixing of the air into the equipment is prevented or restrained, thereby eliminating influence by remaining water content, improving outgassing remove efficiency after cleaning, and enabling remarkable reduction of releasing time after cleaning. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题为了解决在处理设备中不能避免反应室内壁和内部结构物体粘附的问题，需要定期清洗的清洗工作通常使用纯水或IPA（异丙醇）等，并且在设备内部对空气打开的状态下进行手动湿式清洗工作的系统是主要的，水分含量由于长时间的打开和湿洗的影响而留在设备中需要大量的时间才能撤离，撤离到对下一次治疗有影响的状态，直到效果不明显为止。解决方案：提供一种系统，其中干冰用于清洁介质，干冰的喷射机构安装在处理设备中，并且在空气混入设备中的状态下进行清洁防止或抑制，从而消除残留水分的影响，改善清洗后的除气效率，并且可以显着降低清洗后的释放时间。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005049105A Automatic light intensity adjuster and light intensity adjusting method using the same 审中-公开
标题翻译：自动光强度调节器和光强度调整方法
公开(公告)号：JP2005049105A
公开(公告)日：2005-02-24
申请号：JP2003202912
申请日：2003-07-29
申请人： Hitachi Kasado Eng Co Ltd , 日立笠戸エンジニアリング株式会社
发明人： KIMURA SHIZUAKI , FUJII HIROOMI , KAJI TETSUNORI , AKIYAMA HIROSHI , MATANO KATSUJI
IPC分类号： G01N21/73
摘要： PROBLEM TO BE SOLVED: To provide a device employed in a light emitting / spectrum processing system, which automatically adjusts light intensity at a zone of a light transmitting channel ranging from a light receiving section to a CCD mounted in the light emitting / spectrum processing system after detecting the intensity of each wavelength component of emitted light, by using a light intensity adjuster or the like having the function of adjusting the light intensity.
SOLUTION: Data fetched by the CCD of the light emitting / spectrum processing system are previously adjusted automatically by the light intensity adjuster, in consideration of changes in the light intensity of a light emitting source, thereby obtaining the light intensity in accordance with its condition (so that the light intensity is not overflowing nor too low).
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种在发光/光谱处理系统中使用的装置，其自动调节在从光接收部分到安装在发光/发光装置中的CCD的透光通道的区域处的光强度，通过使用具有调节光强度的功能的光强度调节器等，检测发射光的每个波长分量的强度后的光谱处理系统。解决方案：考虑到发光源的光强度的变化，由发光/光谱处理系统的CCD获取的数据预先由光强度调节器自动调节，由此获得根据它的条件（使光强度不溢出也不太低）。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004158890A Method of processing damascene 审中-公开
公开(公告)号：JP2004158890A
公开(公告)日：2004-06-03
申请号：JP2004051187
申请日：2004-02-26
申请人： Hitachi High-Technologies Corp , 株式会社日立ハイテクノロジーズ
发明人： KAJI TETSUNORI , UCHIMAKI YOICHI
IPC分类号： H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To maintain the wiring resistance of fined multilayered wiring at a low level and to improve the performance of an integrated circuit and, at the same time, the productivity of the multilayered wiring.
SOLUTION: In a method of damascene processing, an electrically conductive damascene is formed by embedding copper 115 in a plug section 112 formed in an electrical insulation layer. After a low-k material is etched (a), the etched surface 122 of the plug section 112 is made to become a copper barrier by turning materials on the etched surface to carbon, nitrogen, bromide, boron, reduction, non-crystallization, or modification, performed by combining these treatment, the surface 122 by crashing ions 121 accelerated with a voltage or neutral particles produced by neutralizing the accelerated ions 121 into the etched surface 122, in the same treatment chamber where the low-k material is etched or another treatment chamber after the plug section 112 is transported to the chamber in a vacuum (b). Then the copper 115 is embedded in the plug section 112 (d).
COPYRIGHT: (C)2004,JPO

10. 发明专利

JP2004103971A Method and apparatus for damascene processing, and damascene structure 审中-公开
公开(公告)号：JP2004103971A
公开(公告)日：2004-04-02
申请号：JP2002266371
申请日：2002-09-12
申请人： Hitachi High-Technologies Corp , 株式会社日立ハイテクノロジーズ
发明人： KAJI TETSUNORI , UCHIMAKI YOICHI
IPC分类号： H01L21/768
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76823 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76831
摘要： PROBLEM TO BE SOLVED: To enhance the performance of an integrated circuit by keeping the wiring resistance of an increasingly minaturized multilayer wiring at a low level, and to enhance the productivity of the multilayer wiring.
SOLUTION: The damascene processing apparatus for forming an electroconductive damascene by inlaying a plug portion formed in an insulating film with copper, is provided with; a chamber 151A for giving etching treatment to a low-k member; a chamber 153 for conveying the etched specimen in a vacuum; a chamber 151B, which is provided with a means for receiving the conveyed specimen and a means for applying voltage, for giving a copper barrier treatment by permitting ions accelerated by the application of voltage or neutral particles obtained by neutralizing the accelerated ions, to collide against the etched surface for reformation thereof through carbonization, nitriding, bromination, boronizing, reduction or amorphization, or combination thereof; and a chamber 151C for giving a high vacuum processing to fit copper into the plug portion which has a surface processed in a etching treatment and a copper barrier treatment.
COPYRIGHT: (C)2004,JPO

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