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1. 发明专利

JP2004134471A Semiconductor device and its manufacturing method 审中-公开
公开(公告)号：JP2004134471A
公开(公告)日：2004-04-30
申请号：JP2002295503
申请日：2002-10-09
申请人： Hitachi Device Eng Co Ltd , Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 日立デバイスエンジニアリング株式会社 , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： TOJO SHINJI , KANEMITSU NOBUYA , ICHIHARA SEIICHI , NAKAMURA TOSHIO , AKIMOTO KOJI
IPC分类号： G02F1/1345 , H01L21/60
CPC分类号： H01L2224/16225 , H01L2224/16227 , H01L2224/29082 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/73204 , H01L2224/83101 , H01L2224/83851 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technology by which pads having a prescribed size can be formed and different bumps can be formed on the pads by changing the sizes and arrangement of the bumps in accordance with the mounted form of a semiconductor chip and, in addition, is easily applicable to custom mounting of the chip and can shorten the development TAT. SOLUTION: In a semiconductor device, a semiconductor element circuit and its external electrodes (pads) 4 are formed on the main surface of a semiconductor substrate, and the electrodes (pads) 4 are electrically connected to the wiring (inner leads) of a wiring board through bumps. In the device, the sizes of external electrodes (pads) 5B are made uniform (equalized) and the bumps are formed by changing their sizes and arrangement in accordance with the mounted state of the semiconductor chip. Since probe coordinates can be separated, probe inspections can be performed easily. COPYRIGHT: (C)2004,JPO

2. 发明专利

JP2004158895A Method of manufacturing semiconductor device 有权
公开(公告)号：JP2004158895A
公开(公告)日：2004-06-03
申请号：JP2004060490
申请日：2004-03-04
申请人： Hitachi Ulsi Systems Co Ltd , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社日立超エル・エス・アイ・システムズ
发明人： TOJO SHINJI , KANEMITSU NOBUYA , ICHIHARA SEIICHI
IPC分类号： H01L21/60
CPC分类号： H01L2224/75 , H01L2224/75745 , H01L2924/01322
摘要： PROBLEM TO BE SOLVED: To highly precisely connect a projected electrode of a semiconductor chip with the lead of a film substrate.
SOLUTION: The pitch of inner leads is previously corrected in the stages of designing the film substrate, by considering variations of the lead pitch when the projected electrodes of the semiconductor chip are connected to the inner leads of the film substrate. Namely, the cumulative pitches of all the inner leads in the direction of the long side of the chip installation region C are increased, the inner leads near the center section are furthermore increased. Also, the pitch of the outer leads is previously corrected by considering the variations of the lead pitch when the electrodes of a liquid crystal substrate is connected to the outer leads of the film substrate.
COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2006013421A Semiconductor device and manufacturing method of semiconductor device 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：JP2006013421A
公开(公告)日：2006-01-12
申请号：JP2004350646
申请日：2004-12-03
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ICHIHARA SEIICHI , KANEMITSU NOBUYA , TOJO SHINJI , NAKAMURA TOSHIO
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a packaging technology for coping with finer pitch and a larger number of pins, and a semiconductor device using the packaging technology.
SOLUTION: In the semiconductor device, a semiconductor chip 1C, on which a plurality of bumps 2 are arranged at a periphery portion of principal plane, and a lead 19b formed in COF tape are electrically connected through a plurality of the bumps 2. The plurality of the bumps 2 are formed in such a manner that a plurality of bumps 2a arranged at chip end side and a plurality of bumps 2b arrange at chip center side are alternately disposed each other. A width of the lead 19b connected with the bumps 2b between the bumps 2a is narrower than that of a portion connected with the bumps 2b of the lead 19.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于应对更细的间距和更多数量的引脚的封装技术，以及使用封装技术的半导体器件。解决方案：在半导体器件中，在主平面的周边部分布置有多个凸块2的半导体芯片1C和形成在COF带中的引线19b通过多个凸块2电连接多个凸块2以这样的方式形成，使得布置在芯片端侧的多个凸起2a和布置在芯片中心侧的多个凸块2b彼此交替地布置。与凸块2a之间的凸起2b连接的引线19b的宽度比与引线19的凸起2b连接的部分的宽度窄。（C）2006，JPO＆NCIPI

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