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    • 1. 发明专利
    • Cmos integrated circuit device
    • CMOS集成电路设备
    • JPS60190020A
    • 1985-09-27
    • JP4547184
    • 1984-03-12
    • Hitachi Control Syst Co LtdHitachi Ltd
    • KODAMA KAZUYUKIKITATSUME YOSHIAKIAKIYAMA MASAKAZUISHIKAWA KATSUFUMIOONUMA KUNIHIKO
    • H03K19/0948G01R31/28G06F1/04G10L11/00G10L15/28H03K17/16
    • H03K17/16
    • PURPOSE:To decrease a peak value of a power noise produced at signal switching without incurring the increase in a chip area by retarding a switching timing of plural output signals by a prescribed time at each several signal line bundles. CONSTITUTION:In case of, e.g., a voice recognition CMOSLSI circuit, 20 data lines D are divided into D1 in 6-bit and D2, D3 in 7-bit, the D1 is latched to a memory address register MAR1 in the timing of CK, the D2 is latched to an MAR2 by using a clock CK2 delayed by a delay time of the two stages of inverters INV than the time of the CK, and the D3 is latched in an MAR3 by using a clock CK3 delayed by the delay time of two stages of the INV than the time of the CK2. Thus, six lines are switched in the timing of the CK, seven lines are switched in the timing of the CK2 and seven lines are switched sequentially in the timing of the CK3 in the output circuit. Thus, the peak current produced in the output circuit and power supply is decreased at the switching of data in 20-bit.
    • 目的:降低在信号切换时产生的功率噪声的峰值,而不会在每个几个信号线束处延迟多个输出信号的开关定时预定时间,而不会导致芯片面积的增加。 规定:在例如语音识别CMOSLSI电路的情况下,20条数据线D被分成6位的D1和D2,7位的D3,在CK的定时中将D1锁存到存储器地址寄存器MAR1 通过使用延迟了两级反相器INV的延迟时间的时钟CK2比CK的时间将D2锁存到MAR2,并且通过使用延迟延迟时间的时钟CK3将D3锁存在MAR3中 的两个阶段的INV比CK2的时间。 因此,在CK的定时中切换六条线,在CK2的定时切换七条线,并且在输出电路中的CK3的定时中顺序切换七条线。 因此,在20位的数据切换时,输出电路和电源产生的峰值电流降低。
    • 3. 发明专利
    • VOICE OUTPUT DEVICE
    • JPS6452199A
    • 1989-02-28
    • JP20813387
    • 1987-08-24
    • HITACHI LTDHITACHI CONTROL SYST
    • ISHIKAWA KATSUFUMISHIMIZU NORIKAZU
    • G10L11/00G10L15/06
    • PURPOSE: To obtain a voice output device provided with a simple and inexpensive voice registering function by temporarily storing a voice waveform, displaying the voice waveform on a screen and visually expressing the segmentation of phrases. CONSTITUTION: A voice input waiting state is set up by operation from a keyboard 17. Then a reproducing machine 19 is traveled, a voice input waveform is inputted to an analytical circuit 14, PCM exchange is executed in the circuit 14, and voice analytical data 102 are stored in a voice data temporary storage circuit 11. After ending the writing of the data 102, a control circuit 12 displays the data 102 more than a certain threshold on a display 16. When a voice check key is depressed, voice reproducing data 103 are outputted from an intra- memory address section of the circuit 11 which is indicated by a moved start end cursor and an unmoved final end cursor to a speaker 18 through a reproducing circuit 13. Finally a segmented phrase is outputted from the circuit 11 and written in a voice record storing part 15 together with a start end address and a data count. The operation is repeated to complete the segmentation of pharases.