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1. 发明申请

US20030067018A1 System with meshed power and signal buses on cell array 有权
公开(公告)号：US20030067018A1
公开(公告)日：2003-04-10
申请号：US10315307
申请日：2002-12-10
申请人： Hitachi, Ltd.
发明人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
IPC分类号： H01L027/10
CPC分类号： G11C5/063 , G11C5/025 , G11C5/14 , G11C7/065 , G11C7/18 , G11C8/14 , H01L23/5286 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

2. 发明申请

US20030043680A1 Semiconductor memory circuit 有权
标题翻译：半导体存储电路
公开(公告)号：US20030043680A1
公开(公告)日：2003-03-06
申请号：US10190480
申请日：2002-07-09
申请人： Hitachi, Ltd.
发明人： Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
IPC分类号： G11C005/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
摘要翻译：本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。

3. 发明申请

US20040129974A1 SYSTEM WITH MESHED POWER AND SIGNAL BUSES ON CELL ARRAY 失效
标题翻译：具有电力阵列的系统和信号阵列上的信号总线
公开(公告)号：US20040129974A1
公开(公告)日：2004-07-08
申请号：US10728682
申请日：2003-12-05
申请人： Hitachi, Ltd. , Texas Instruments Incorporated
发明人： Goro Kitsukawa , Takesada Akiba , Hiroshi Otori , William R. McKee , Jeffrey E. Koelling , Troy H. Herndon
IPC分类号： H01L029/76
CPC分类号： G11C5/063 , G11C5/025 , G11C5/14 , G11C7/065 , G11C7/18 , G11C8/14 , H01L23/5286 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.
摘要翻译：一种用于在阵列型集成电路上提供网状电源和信号总线系统的方法和装置，其使电路的尺寸最小化。与现有技术不同，用于网状系统的通孔被放置在电池阵列以及外围电路中。网格系统的功率和信号总线跨阵列在垂直和水平方向上运行，使得所有垂直总线位于一个金属层中，并且所有水平总线位于另一个金属层中。使用位于阵列中的通孔将一层的总线连接到另一层的适当总线。一旦连接，总线延伸到适当的感应放大器驱动器。通过实现分级字线结构的改进的子解码器电路来促进该方法和装置。

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