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1. 发明申请

US20080204067A1 SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME 失效
标题翻译：同步半导体器件及其检测系统及其方法
公开(公告)号：US20080204067A1
公开(公告)日：2008-08-28
申请号：US12112782
申请日：2008-04-30
申请人： Hiroyuki SUGAMOTO , Hidetoshi Tanaka , Yasushige Ogawa
发明人： Hiroyuki SUGAMOTO , Hidetoshi Tanaka , Yasushige Ogawa
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译：本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

2. 发明授权

US07378863B2 Synchronous semiconductor device, and inspection system and method for the same 失效
标题翻译：同步半导体器件及其检测系统及方法相同
公开(公告)号：US07378863B2
公开(公告)日：2008-05-27
申请号：US11014789
申请日：2004-12-20
申请人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
发明人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
IPC分类号： G01R31/28
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译：本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

3. 发明申请

US20100052727A1 SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME 审中-公开
标题翻译：同步半导体器件及其检测系统及其方法
公开(公告)号：US20100052727A1
公开(公告)日：2010-03-04
申请号：US12614713
申请日：2009-11-09
申请人： Hiroyuki SUGAMOTO , Hidetoshi Tanaka , Yasushige Ogawa
发明人： Hiroyuki SUGAMOTO , Hidetoshi Tanaka , Yasushige Ogawa
IPC分类号： G01R31/28
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carry out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will resent a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译：本发明提供一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地进行老化应力试验。具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号重新发出。同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

4. 发明授权

US07663392B2 Synchronous semiconductor device, and inspection system and method for the same 失效
标题翻译：同步半导体器件及其检测系统及方法相同
公开(公告)号：US07663392B2
公开(公告)日：2010-02-16
申请号：US12112782
申请日：2008-04-30
申请人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
发明人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
IPC分类号： G01R31/28 , G11C7/00
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译：本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

5. 发明申请

US20050111293A1 Synchronous semiconductor device, and inspection system and method for the same 失效
标题翻译：同步半导体器件及其检测系统及方法相同
公开(公告)号：US20050111293A1
公开(公告)日：2005-05-26
申请号：US11014789
申请日：2004-12-20
申请人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
发明人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
IPC分类号： G01R31/28 , G01R31/317 , G11C8/08 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/34 , G11C8/00
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
摘要翻译：本发明提供了一种同步半导体装置，其适用于提高对装置的电应力的效率，检查系统及其检查方法，以便有效地执行老化压力试验。具有访问命令输入的命令锁存电路将输出与外部时钟同步的低电平脉冲。脉冲将通过测试模式序列电路的NAND门和公共NAND门，以输出低电平的内部预充电信号，这将使来自控制电路的字线激活信号复位。同时，通过NAND门的内部预充电信号将被内部定时器延迟预定时间段，以通过NAND门输出低电平内部有效信号，该低电平内部有效信号将设置来自控制电路的字线激活信号。

6. 发明授权

US06891393B2 Synchronous semiconductor device, and inspection system and method for the same 失效
公开(公告)号：US06891393B2
公开(公告)日：2005-05-10
申请号：US10373869
申请日：2003-02-27
申请人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
发明人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Ogawa
IPC分类号： G01R31/28 , G01R31/317 , G11C8/08 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/34
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

7. 发明授权

US06559669B2 Synchronous semiconductor device, and inspection system and method for the same 有权
公开(公告)号：US06559669B2
公开(公告)日：2003-05-06
申请号：US09820715
申请日：2001-03-30
申请人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Tanaka
发明人： Hiroyuki Sugamoto , Hidetoshi Tanaka , Yasushige Tanaka
IPC分类号： G01R3128
CPC分类号： G11C8/08 , G01R31/31701 , G11C29/34
摘要： The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

8. 发明授权

US08262766B2 Method for reducing chromium containing raw material 失效
标题翻译：减少含铬原料的方法
公开(公告)号：US08262766B2
公开(公告)日：2012-09-11
申请号：US12543798
申请日：2009-08-19
申请人： Hiroshi Sugitatsu , Hidetoshi Tanaka , Takao Harada , Itsuo Miyahara , Isao Kobayashi
发明人： Hiroshi Sugitatsu , Hidetoshi Tanaka , Takao Harada , Itsuo Miyahara , Isao Kobayashi
IPC分类号： C21B11/00
CPC分类号： C22B5/10 , C21B13/10 , C22B1/244 , C22B34/32 , Y02P10/136
摘要： An object of the present invention is to provide a method for reducing a chromium-containing material at a high chromium reduction degree. In the method of the present invention, a mixture of a feedstock containing chromium oxide and a carbonaceous reductant is heated and reduced by radiation heating in a moving hearth furnace. The average rate of raising the temperature of the mixture in the reduction is preferably 13.96° C./s or higher in the period from the initiation of the radiation heating of the mixture until the mixture reaches 1,114° C.
摘要翻译：本发明的目的是提供一种在高铬还原度下还原含铬材料的方法。在本发明的方法中，通过在移动的炉床炉中的辐射加热来加热和还原含有氧化铬和碳质还原剂的原料的混合物。在从混合物的辐射加热开始到混合物达到1114℃之间的时间内，还原中混合物的温度升高的平均速率优选为13.96℃/秒或更高。

9. 发明授权

US07438730B2 Method of producing iron oxide pellets 失效
标题翻译：生产氧化铁丸的方法
公开(公告)号：US07438730B2
公开(公告)日：2008-10-21
申请号：US11378269
申请日：2006-03-20
申请人： Yasuhiko Igawa , Jun Jimbo , Hidetoshi Tanaka , Shoichi Kikuchi , Takao Harada , Osamu Tsuchiya , Shuzo Ito , Isao Kobayashi
发明人： Yasuhiko Igawa , Jun Jimbo , Hidetoshi Tanaka , Shoichi Kikuchi , Takao Harada , Osamu Tsuchiya , Shuzo Ito , Isao Kobayashi
IPC分类号： C01B31/14
CPC分类号： C05D9/02 , C05G3/0047 , C21B13/0046 , C21B13/105 , C22B1/2406 , C22B1/243 , C22B1/244 , C22B1/245 , C22B13/10 , Y02P10/212
摘要： A method for producing an iron oxide pellet including the steps of adding water to a raw material mixture comprising iron oxide which serves as a primary component, a carbonaceous material in an amount sufficient for reducing the iron oxide, an organic binder in an amount sufficient for binding the iron oxide and the carbonaceous material, and an inorganic coagulant in an amount of not less than 0.05 mass % and less than 1 mass %; pelletizing the resultant mixture to thereby obtain a green pellet; and drying the green pellet until the moisture content is reduced to equal to or less than 1.0 mass %. The thus-produced iron oxide pellet is charged in a reducing furnace for reduction to thereby obtain a reduced iron pellet.
摘要翻译：一种氧化铁颗粒的制造方法，其特征在于，包括以下步骤：将水作为主要组分的含有氧化铁的原料混合物，足以还原氧化铁的碳质材料，结合铁氧化物和碳质材料，无机凝结剂的量不小于0.05质量％且小于1质量％; 将所得混合物造粒，得到生球团块; 并干燥绿色颗粒，直到含水量降低至1.0质量％以下。将由此生产的氧化铁颗粒装入还原炉中进行还原，从而获得还原铁颗粒。

10. 发明申请

US20070251294A1 SENSOR NODE FOR IMPACT DETECTION 失效
标题翻译：用于冲击检测的传感器节点
公开(公告)号：US20070251294A1
公开(公告)日：2007-11-01
申请号：US11211485
申请日：2005-08-26
申请人： Hidetoshi Tanaka , Kei Suzuki
发明人： Hidetoshi Tanaka , Kei Suzuki
IPC分类号： G01N3/30
CPC分类号： G01P15/0922 , G01P15/0891
摘要： The invention is intended to provide a technique regarding sensor nodes for impact detection to enable the intensities of impacts to be determined in a multi-value or analog mode and to reduce the power consumption of sensor nodes. The sensor node is provided with a shock detection sensor comprising a piezoelectric element unit which generates an electric charge corresponding to an external impact, a capacitor which rectifies and accumulates the electric charge so generated, and a voltage detector which operates on the accumulated power and externally outputs a signal when the accumulated voltage reaches a preset level; a stand-by control object section which is caused by the external signal to return from a stand-by state and to operate; and a power supply which feeds power to the stand-by control object section, wherein the operation of the stand-by control object section is triggered by the signal of impact detected by the piezoelectric element unit.
摘要翻译：本发明旨在提供一种关于用于冲击检测的传感器节点的技术，以使得能够以多值或模拟模式确定冲击的强度并降低传感器节点的功率消耗。传感器节点设有一个震动检测传感器，它包括一个压电元件单元，该压电元件单元产生一个与外部冲击相对应的电荷;一个电容器，用于整流和累积如此产生的电荷;以及一个电压检测器，其对累积功率和外部当累积电压达到预设电平时，输出信号; 由外部信号引起的备用控制对象部分从待机状态返回并进行操作; 以及向备用控制对象部供电的电源，其中，由压电元件单元检测到的冲击信号触发待机控制对象部的动作。

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