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1. 发明授权

US07151027B1 Method and device for reducing interface area of a memory device 有权
标题翻译：用于减少存储器件的接口面积的方法和装置
公开(公告)号：US07151027B1
公开(公告)日：2006-12-19
申请号：US10859369
申请日：2004-06-01
申请人： Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
发明人： Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11536 , H01L27/11548
摘要： A method and device for reducing interface area of a memory device. A poly-2 layer is formed above a substrate at an interface between a memory array and a periphery of the memory device. The poly-2 layer is etched proximate to the memory array. The poly-2 layer is etched proximate to the periphery such that a portion of the poly-2 layer remains at the interface.
摘要翻译：一种用于减少存储器件的接口面积的方法和装置。在存储器阵列和存储器件的外围之间的界面处，在衬底上形成多晶硅层2。聚二层蚀刻到存储器阵列附近。聚二层被蚀刻到外围附近，使得多2层的一部分保留在界面处。

2. 发明申请

US20050151265A1 Efficient use of wafer area with device under the pad approach 审中-公开
标题翻译：利用垫片方式下的设备有效利用晶圆区域
公开(公告)号：US20050151265A1
公开(公告)日：2005-07-14
申请号：US10758148
申请日：2004-01-14
申请人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun , Darlene Hamilton
发明人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun , Darlene Hamilton
IPC分类号： G06F17/50 , H01L23/485 , H01L27/02 , H01L23/48 , H01L21/44
CPC分类号： H01L27/0203 , H01L24/05 , H01L24/06 , H01L2224/02166 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/14 , H01L2924/19043 , H01L2924/00014
摘要： More efficient use of silicon area is achieved by incorporating an active device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is below the first metal layer. The active device resides in the substrate below the second metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the active component. Subsequent metal layers can be arranged between the first and second metal layers.
摘要翻译：通过在半导体结构的焊盘区域的下方并入有源器件来实现硅面积的更有效的使用。焊盘区域包括在其上方具有第一金属层的基板。第二金属层位于第一金属层的下方。有源器件位于第二金属层下方的衬底中。电介质层分离第一和第二金属层。电介质层内的通孔电耦合第一和第二金属层。 A通道连接到活动组件。随后的金属层可以布置在第一和第二金属层之间。

3. 发明授权

US07632749B1 Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer 有权
标题翻译：具有电耦合的焊盘金属层和下金属层的半导体器件，而在焊盘金属层的中心区域下方的下金属层中形成孔
公开(公告)号：US07632749B1
公开(公告)日：2009-12-15
申请号：US10823970
申请日：2004-04-13
申请人： Hiroyuki Ogawa , Yider Wu , Nian Yang , Kuo-Tung Chang , Yu Sun
发明人： Hiroyuki Ogawa , Yider Wu , Nian Yang , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05554 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要： A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.
摘要翻译：公开并提供了半导体器件。半导体器件包括具有周边区域和中心区域的焊盘金属层。此外，半导体器件具有在焊盘金属层的中心区域下方具有多个孔的下部金属层。此外，在焊盘金属层和下金属层之间形成层间电介质。在一个实施例中，半导体器件还包括形成在层间电介质中的多个通孔。通孔电连接焊盘金属层和下部金属层。另外，通孔位于垫金属层的周边区域的下方。

4. 发明授权

US07019366B1 Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance 有权
标题翻译：硅结构的静电放电性能，有效利用垫下方的静电放电保护装置的面积，调整通孔配置，以控制漏极结电阻
公开(公告)号：US07019366B1
公开(公告)日：2006-03-28
申请号：US10758173
申请日：2004-01-14
申请人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
发明人： Nian Yang , Hiroyuki Ogawa , Yider Wu , Kuo-Tung Chang , Yu Sun
IPC分类号： H01L23/62
CPC分类号： H01L27/0251
摘要： More efficient use of silicon area is achieved by incorporating an electrostatic discharge protective (ESDP) device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is above the first metal layer. The ESDP device resides in the substrate below the first metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the ESDP component. Subsequent metal layers can be arranged between the first and second metal layers. The Ohmic value of the resistance component of the ESDP device can be set during fabrication by fixing a number of individual via components, arranged electrically in parallel, by fixing the cross sectional area of the via components, and/or by fixing the length of the via components.
摘要翻译：通过在半导体结构的焊盘区域的下方并入静电放电保护（ESDP）器件来实现硅面积的更有效的使用。焊盘区域包括在其上方具有第一金属层的基板。第二金属层位于第一金属层之上。 ESDP设备位于第一金属层下方的基板中。电介质层分离第一和第二金属层。电介质层内的通孔电耦合第一和第二金属层。 A通道连接到ESDP组件。随后的金属层可以布置在第一和第二金属层之间。 ESDP装置的电阻部件的欧姆值可以在制造期间通过固定多个单独的通孔部件，通过固定通孔部件的横截面面积和/或固定长度通过组件。

5. 发明授权

US07301193B2 Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元中低Vss电阻和减少DIBL的结构和方法
公开(公告)号：US07301193B2
公开(公告)日：2007-11-27
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela T. Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

6. 发明申请

US20050164450A1 Structure and method for low Vss resistance and reduced dibl in a floating gate memory cell 有权
标题翻译：浮动栅极存储单元的低Vss电阻和二极管的结构和方法
公开(公告)号：US20050164450A1
公开(公告)日：2005-07-28
申请号：US10762445
申请日：2004-01-22
申请人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
发明人： Shenqing Fang , Timothy Thurgate , Kuo-Tung Chang , Richard Fastow , Angela Hui , Kazuhiro Mizutani , Kelwin Ko , Hiroyuki Kinoshita , Yu Sun , Hiroyuki Ogawa
IPC分类号： H01L21/28 , H01L21/336 , H01L21/74 , H01L29/417 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/743 , H01L29/41766 , H01L29/66636
摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.
摘要翻译：根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

7. 发明申请

US20070026675A1 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US20070026675A1
公开(公告)日：2007-02-01
申请号：US11193409
申请日：2005-08-01
申请人： Unsoon Kim , Angela Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L21/302
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

8. 发明授权

US08133801B1 Method for forming a semiconducting layer with improved gap filling properties 有权
标题翻译：用于形成具有改善的间隙填充性能的半导体层的方法
公开(公告)号：US08133801B1
公开(公告)日：2012-03-13
申请号：US11189875
申请日：2005-07-27
申请人： Rinji Sugino , Yider Wu , Minh Van Ngo , Jeffrey Sinclair Glick , Kuo-Tung Chang
发明人： Rinji Sugino , Yider Wu , Minh Van Ngo , Jeffrey Sinclair Glick , Kuo-Tung Chang
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/0237 , H01L21/02488 , H01L21/02595 , H01L21/0262 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568
摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.
摘要翻译：一种制造存储器件的方法包括在衬底上形成第一介电层，在第一介电层上形成电荷存储元件，并在电荷存储元件上形成栅极间电介质。该方法还包括使用含氯的反应物在栅极间电介质上沉积硅控制栅极层。

9. 发明授权

US06919247B1 Method of fabricating a floating gate 失效
标题翻译：制造浮栅的方法
公开(公告)号：US06919247B1
公开(公告)日：2005-07-19
申请号：US10655936
申请日：2003-09-04
申请人： Yider Wu , Kuo-Tung Chang
发明人： Yider Wu , Kuo-Tung Chang
IPC分类号： H01L21/28 , H01L21/8247
CPC分类号： H01L21/28273
摘要： A method of fabricating a floating gate for a semiconductor device is disclosed and provided. According to this method, an undoped polycrystalline silicon layer is deposited on a tunnel oxide layer. The undoped polycrystalline silicon layer has a first thickness. Moreover, a doped polycrystalline silicon layer is deposited on the undoped polycrystalline silicon layer. The doped polycrystalline silicon layer has a second thickness. The undoped polycrystalline silicon layer and the doped polycrystalline silicon layer form the floating gate having a third thickness. In an embodiment, the semiconductor device is a flash memory device.
摘要翻译：公开并提供了制造用于半导体器件的浮栅的方法。根据该方法，在隧道氧化物层上沉积未掺杂的多晶硅层。未掺杂的多晶硅层具有第一厚度。此外，掺杂的多晶硅层沉积在未掺杂的多晶硅层上。掺杂多晶硅层具有第二厚度。未掺杂多晶硅层和掺杂多晶硅层形成具有第三厚度的浮动栅极。在一个实施例中，半导体器件是闪存器件。

10. 发明授权

US08802537B1 System and method for improving reliability in a semiconductor device 有权
标题翻译：用于提高半导体器件的可靠性的系统和方法
公开(公告)号：US08802537B1
公开(公告)日：2014-08-12
申请号：US11189874
申请日：2005-07-27
申请人： Yider Wu , Unsoon Kim , Kuo-Tung Chang , Harpreet Sachar
发明人： Yider Wu , Unsoon Kim , Kuo-Tung Chang , Harpreet Sachar
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/02057
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。存储器件被预先清洁以准备用于其上形成氧化物的存储器件的表面，其中清洁存储器件去除沟槽相对侧上的阻挡氧化物层的部分。在沟槽的相对侧上修整氮化物层。在沟槽中形成衬里氧化物层。

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