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1. 发明授权

US5216424A Binary data converter 失效
标题翻译：二进制数据转换器
公开(公告)号：US5216424A
公开(公告)日：1993-06-01
申请号：US707145
申请日：1991-05-31
申请人： Hiroyuki Kouno , Sumitaka Takeuchi , Keisuke Okada
发明人： Hiroyuki Kouno , Sumitaka Takeuchi , Keisuke Okada
IPC分类号： G06F7/38 , G06F7/48 , H03M7/04
CPC分类号： H03M7/04 , G06F7/48
摘要： A binary data converter is adapted to convert a positive binary data into a negative binary data represented by a complement on two and vice verse. The conversion is effected as follows. A least significant bit of an inputted binary data is outputted as the least significant bit of the converted binary date as it is. With respect to bit signal other than the least significant bit, respective input bit signals less significant than the corresponding input bit signal are ORed. Depending on the result thereof, inverted or non-inverted signals of the corresponding input bit signals are outputted as the bit signals of the converted binary data. Therefore, carry delay is not generated, and thus the operation speed can be increased. Further, the simple circuit structures can reduce the number of required elements.
摘要翻译：二进制数据转换器适于将正二进制数据转换成由二进制补码表示的负二进制数据。转换如下进行。输入的二进制数据的最低有效位作为转换的二进制日期的最低有效位被原样输出。对于除了最低有效位之外的位信号，相对于相应的输入位信号而言，相对于输入位信号的有效值为“或”。根据其结果，相应的输入位信号的反相或非反转信号作为转换的二进制数据的位信号被输出。因此，不产生进位延迟，能够提高运转速度。此外，简单的电路结构可以减少所需元件的数量。

2. 发明授权

US4903027A A/D converter comprising encoder portion having function of multiplying analogue input by digital input 失效
标题翻译： A / D转换器包括具有通过数字输入将模拟输入相乘的编码器部分
公开(公告)号：US4903027A
公开(公告)日：1990-02-20
申请号：US159405
申请日：1988-02-11
申请人： Sumitaka Takeuchi , Keisuke Okada
发明人： Sumitaka Takeuchi , Keisuke Okada
IPC分类号： H03M1/14 , G06J1/00 , H03M1/36
CPC分类号： G06J1/00 , H03M1/365
摘要： An A/D converter of a serial-parallel comparison type has both multiplying functions of an analog input data and a digital input data. The analog input data V.sub.X is converted into a digital code I.sub.c corresponding to two more significant digits, by a first parallel comparing portion and a first determining circuit, and converted into a digital code I.sub.f corresponding to two less significant digits by a second parallel comparing portion and a second determining circuit. The digital codes I.sub.c and I.sub.f are alternately applied to a control circuit by a first selector circuit. Two more significant bits R.sub.c and two less significant bits R.sub.f of a 4-bit digital input data are respectively applied to a control signal generating circuit by a second selector circuit. Multiplications of R.sub.c I.sub.c, RfIc, R.sub.c I.sub.f and R.sub.f I.sub.f are serially performed within the time period of one conversion by the control signal generating circuit and the control circuit. The multiplied results are shifted four bits, two bits, two bits and 0 bits, respectively, and then, added to each other. As a result, the product of the analogue input data and the digital input data is calculated.
摘要翻译：并行比较型的A / D转换器具有模拟输入数据和数字输入数据的乘法功能。通过第一并行比较部分和第一确定电路将模拟输入数据VX转换成对应于两个有效数字的数字代码Ic，并且被转换成数字代码如果对应于由第二并行比较部分的两个较低有效数字和第二确定电路。数字代码Ic和If由第一选择器电路交替地施加到控制电路。 4位数字输入数据的两个有效位Rc和两个较低有效位Rf由第二选择器电路分别施加到控制信号发生电路。 RcIc，RfIc，RcIf和RfIf的乘法在控制信号发生电路和控制电路的一次转换的时间段内连续执行。相乘的结果分别移位四位，两位，两位和0位，然后相加。结果，计算模拟输入数据和数字输入数据的乘积。

3. 发明授权

US4896284A Semiconductor integrated circuit for multiplying analog and digital values 失效
标题翻译：用于将模拟和数字值相乘的半导体集成电路
公开(公告)号：US4896284A
公开(公告)日：1990-01-23
申请号：US226636
申请日：1988-08-01
申请人： Sumitaka Takeuchi , Keisuke Okada , Masatoshi Kimura
发明人： Sumitaka Takeuchi , Keisuke Okada , Masatoshi Kimura
IPC分类号： H03M1/36 , G06F7/52 , G06J1/00
CPC分类号： G06J1/00 , G06F7/523 , H03M1/365
摘要： A semiconductor integrated circuit so arranged that selection is made out of output signals of a decision circuit which determines the levels of analog values inputted as an object for multiplication and multiplication is carried out with respect to the selected signal and the digital value inputted as an object for multiplication, the result of the multiplication being added with the digital value as shifted to the higher position of specified bits, a multiplication result being thereby calculated with respect to the analog value and the digital value, whereby the required area of wiring connections is reasonably reduced and faster operation is assured.
摘要翻译：一种半导体集成电路，其被配置为根据所选择的信号和作为对象输入的数字值，执行确定作为乘法和乘法对象输入的模拟值的电平的判定电路的输出信号的选择为了乘法，乘法的结果被加上移动到指定位的较高位置的数字值，由此相对于模拟值和数字值计算乘法结果，由此所需的接线连接面积是合理的减少和更快的操作得到保证。

4. 发明授权

US4918453A A/D converter having multiplication function 失效
标题翻译：具有乘法功能的A / D转换器
公开(公告)号：US4918453A
公开(公告)日：1990-04-17
申请号：US181338
申请日：1988-04-14
申请人： Masatoshi Kimura , Sumitaka Takeuchi , Keisuke Okada
发明人： Masatoshi Kimura , Sumitaka Takeuchi , Keisuke Okada
IPC分类号： H03M1/36 , G06J1/00
CPC分类号： G06J1/00 , H03M1/365
摘要： A semiconductor integrated circuit which is comprised of the following; a plurality of comparators which respectively compare analog values inputted for multiplication with individual reference voltages respectively, multiplication means which controls values outputted from those plural comparators by applying signals corresponding to digital values inputted for multiplication and outputs the product of the values outputted from those plural comparators and the digital values, and a complement operation circuit which converts the value outputted from multiplication means into complement when the digital value is negative.
摘要翻译：一种半导体集成电路，由以下组成：多个比较器分别比较输入的各个参考电压与各个参考电压相乘所输入的乘法运算的乘法运算装置，通过应用与输入乘法运算的数字值对应的信号来控制从这些多个比较器输出的值，并输出从这些多个比较器输出的值的乘积和数字值，以及当数字值为负时将从乘法装置输出的值转换为补码的补码运算电路。

5. 发明授权

US4866443A A/D converter having multiplication function 失效
标题翻译：具有乘法功能的A / D转换器
公开(公告)号：US4866443A
公开(公告)日：1989-09-12
申请号：US111047
申请日：1987-10-21
申请人： Keisuke Okada , Sumitaka Takeuchi
发明人： Keisuke Okada , Sumitaka Takeuchi
IPC分类号： H03M1/36 , G06J1/00 , H03M1/00
CPC分类号： G06J1/00 , H03M1/361
摘要： A semiconductor integrated circuit includes a plurality of comparators for comparing an analog input with reference voltage or voltages, holding means for holding a digital value, and control means for controlling the outputs of the plurality of comparators by a control signal responsive to the digital value to output the multiplication result of the output values of the plurality of comparators and the digital value. Thus, the integrated circuit can construct a circuit having functions of an A/D converter and a multiplier on one chip.
摘要翻译：半导体集成电路包括用于将模拟输入与参考电压或电压进行比较的多个比较器，用于保持数字值的保持装置和用于通过响应于数字值的控制信号来控制多个比较器的输出的控制装置输出多个比较器的输出值的相乘结果和数字值。因此，集成电路可以在一个芯片上构造具有A / D转换器和乘法器的功能的电路。

6. 发明授权

US5253194A Digital multiplier 失效
标题翻译：数字乘法器
公开(公告)号：US5253194A
公开(公告)日：1993-10-12
申请号：US866708
申请日：1992-04-10
申请人： Sumitaka Takeuchi , Keisuke Okada
发明人： Sumitaka Takeuchi , Keisuke Okada
IPC分类号： G06F7/533 , G06F7/52 , G06F7/523 , G06F7/53
CPC分类号： G06F7/53
摘要： A decode circuit decodes digital signals X1 and X0 as multiplicand to output decoded signals A0-A3. One of these decoded signals A3-A0 is set to be logic 1 in accordance with a value of a multiplicand. A logical operation circuit includes a plurality of operation circuits. Each logical operation circuit performs an independent operation for obtaining a logical value of each bit of the digital signal which is a multiplication result, based on the decoded signals A0-A3 and the digital signals R1 and R0 as a multiplier. Therefore, a result of an operation of a certain bit does not affect results of operations of other bits, so that the logical operation of each bit can be conducted without waiting termination of the logical operations of other bits, which enables high-speed multiplications.
摘要翻译：解码电路将数字信号X1和X0解码为被乘数，以输出解码信号A0-A3。根据被乘数的值将这些解码信号A3-A0中的一个设置为逻辑1。逻辑运算电路包括多个运算电路。每个逻辑运算电路基于解码信号A0-A3和数字信号R1和R0作为乘法器执行用于获得作为乘法结果的数字信号的每个比特的逻辑值的独立操作。因此，某位的操作结果不影响其他位的操作结果，从而可以在不等待终止其他位的逻辑运算的情况下进行每个位的逻辑运算，从而实现高速乘法运算。

7. 发明授权

US4982354A Digital finite impulse response filter and method 失效
标题翻译：数字有限脉冲响应滤波器及方法
公开(公告)号：US4982354A
公开(公告)日：1991-01-01
申请号：US204956
申请日：1988-05-31
申请人： Sumitaka Takeuchi , Keisuke Okada
发明人： Sumitaka Takeuchi , Keisuke Okada
IPC分类号： G06F7/60 , H03H17/02 , H03H17/06
CPC分类号： H03H17/06 , H03H17/0223
摘要： An input analogue signal is converted to a two-valued signal and then it is supplied to each encoder. Each gate signal forming circuit forms a gate signal based on an input digital signal. Each encoder encodes the above stated two-valued signal, an encoding function thereof being determined based on the above stated gate signal. As a result, each encoder outputs a result of multiplication of the two-valued signal and the digital signal in the form of a binary digital signal.
摘要翻译：输入模拟信号被转换为二值信号，然后提供给每个编码器。每个门信号形成电路基于输入数字信号形成门信号。每个编码器对上述两值信号进行编码，其编码功能基于上述门信号确定。结果，每个编码器输出二值数字信号形式的二值信号和数字信号的相乘结果。

8. 发明申请

US20110089827A1 PLASMA DISPLAY PANEL 审中-公开
标题翻译：等离子显示面板
公开(公告)号：US20110089827A1
公开(公告)日：2011-04-21
申请号：US12991867
申请日：2009-05-15
申请人： Hiroto Yanagawa , Hiroyuki Yamakita , Kiyoshi Hishimotodani , Keisuke Okada
发明人： Hiroto Yanagawa , Hiroyuki Yamakita , Kiyoshi Hishimotodani , Keisuke Okada
IPC分类号： H01J17/49 , H01J9/24
CPC分类号： H01J11/12 , H01J9/02 , H01J11/24 , H01J11/32 , H01J2211/245 , H01J2211/323
摘要： The present invention provides a PDP especially having a high definition or super high definition cell structure and realizing excellent image display performance by obtaining light-emitting efficiency as favorable as or more favorable than conventional PDPs while suppressing discharge voltage rise.Therefore, strip-shaped display electrodes 4 and 5 of a PDP 1 are respectively composed of a combination of a transparent electrode 41 and a bus electrode 42 and a combination of a transparent electrode 51 and a bus electrode 52. An electrode gap d between electrodes 41 and 51 falls in a range of 5 μm to 60 μm. A ratio of a total surface area of the electrodes 41 and 51 to a total surface area of discharge cells falls in a range of 0.6 to 0.92. Thus, a discharge start length is larger than the electrode gap d. A product of a total pressure P of a discharge gas and the electrode gap d falls in a range of 13.33 Pa·cm to 133.3 Pa·cm. The discharge gas consists of xenon of 100%. The total pressure P of the discharge gas falls in a range of 2.0 kPa to 53.3 kPa. Thus, a start point of discharge is longer than electrode gap d.
摘要翻译：本发明提供了一种特别是具有高清晰度或超高分辨率单元结构的PDP，并且通过在抑制放电电压上升的同时获得优于常规PDP的发光效率而实现优异的图像显示性能。因此，PDP1的带状显示电极4和5分别由透明电极41和总线电极42的组合以及透明电极51和总线电极52的组合构成。电极间的电极间隙d 41和51落在5μm至60μm的范围内。电极41和51的总表面积与放电单元的总表面积的比率落在0.6至0.92的范围内。因此，放电开始长度大于电极间隙d。放电气体的总压力P与电极间隙d的乘积在13.33Pa·cm〜133.3Pa·cm的范围内。放电气体由100％的氙组成。排出气体的总压力P在2.0kPa〜53.3kPa的范围内。因此，放电的起始点比电极间隙d长。

9. 发明授权

US07260697B2 Data storage device and method of erasing data stored in the data storage device 有权
标题翻译：数据存储装置和擦除存储在数据存储装置中的数据的方法
公开(公告)号：US07260697B2
公开(公告)日：2007-08-21
申请号：US10284257
申请日：2002-10-31
申请人： Keisuke Okada
发明人： Keisuke Okada
IPC分类号： G06F9/312 , G06F1/24
CPC分类号： G06F21/80 , G06F2221/2143
摘要： A recording medium stores data supplied from an external device. A memory stores an erase program for executing erasing of the data stored in the recording medium. An erasing unit erases the data stored in the recording medium in accordance with the erase program stored in the memory, in accordance with a start instruction for instructing a start of erasing the data supplied from the external device.
摘要翻译：记录介质存储从外部设备提供的数据。存储器存储用于执行擦除存储在记录介质中的数据的擦除程序。根据用于指示开始擦除从外部设备提供的数据的开始指令，擦除单元根据存储在存储器中的擦除程序擦除存储在记录介质中的数据。

10. 发明申请

US20070013312A1 Plasma display panel and process for producing the same 失效
标题翻译：等离子显示面板及其制造方法
公开(公告)号：US20070013312A1
公开(公告)日：2007-01-18
申请号：US11484590
申请日：2006-07-12
申请人： Tomohiro Okumura , Hiroyuki Yamakita , Noriyasu Echigo , Mitsuo Saitoh , Junko Asayama , Keisuke Okada
发明人： Tomohiro Okumura , Hiroyuki Yamakita , Noriyasu Echigo , Mitsuo Saitoh , Junko Asayama , Keisuke Okada
IPC分类号： H01J17/49 , H01J11/02
CPC分类号： H01J9/02 , H01J11/12 , H01J11/38
摘要： There are provided a PDP having a higher luminous efficiency and a process for producing the same. In a plasma display panel filled with a discharge gas between a front plate and a rear plate opposed to each other, the front plate 100 comprises a glass substrate 1, electrodes 2 (transparent electrodes 2a and bus electrodes 2b) on the glass substrate 1, the first dielectric layer 4 covering the electrodes 2 and the glass substrate 1 and containing a fluorine atom, the second dielectric layer 5 covering the first dielectric layer 4 and containing a fluorine atom at a less amount than that in the first dielectric layer 4, and a protective layer 6 covering the second dielectric layer 5.
摘要翻译：提供了具有较高发光效率的PDP及其制造方法。在前面板和背板之间填充有放电气体的等离子体显示面板中，前板100包括玻璃基板1，玻璃基板上的电极2（透明电极2a和总线电极2b）如图1所示，覆盖电极2和玻璃基板1并含有氟原子的第一电介质层4，覆盖第一电介质层4并且含有比第一电介质层4中的氟原子少的氟原子的第二电介质层5 以及覆盖第二电介质层5的保护层6。

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