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1. 发明申请

US20070226672A1 Layout determination method, method of manufacturing semiconductor devices, and computer readable program 有权
标题翻译：布局确定方法，制造半导体器件的方法以及计算机可读程序
公开(公告)号：US20070226672A1
公开(公告)日：2007-09-27
申请号：US11509617
申请日：2006-08-25
申请人： Hiroshi Takita , Takashi Maruyama
发明人： Hiroshi Takita , Takashi Maruyama
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5072
摘要： A layout determination method determines a layout of semiconductor devices that are to be created on a substrate by carrying out an exposure process. The layout determination method determines a number of semiconductor devices to be created on one substrate, based on exposure data of the semiconductor devices, a time limit of delivery of the semiconductor devices and a number of substrates to be used for production of the semiconductor devices, obtains coordinates of semiconductor devices arrangeable on the substrate, based on the exposure data, and determines the layout of the semiconductor devices to be created on the substrate, based on the exposure data, the number of semiconductor devices and the coordinates of the semiconductor devices.
摘要翻译：布局确定方法通过执行曝光处理来确定要在基板上创建的半导体器件的布局。布局确定方法基于半导体器件的曝光数据，半导体器件的传送时间限制和用于制造半导体器件的基板的数量来确定要在一个基板上产生的半导体器件的数量，基于曝光数据获得可布置在衬底上的半导体器件的坐标，并且基于曝光数据，半导体器件的数量和半导体器件的坐标来确定要在衬底上产生的半导体器件的布局。

2. 发明授权

US07587703B2 Layout determination method, method of manufacturing semiconductor devices, and computer readable program 有权
标题翻译：布局确定方法，制造半导体器件的方法以及计算机可读程序
公开(公告)号：US07587703B2
公开(公告)日：2009-09-08
申请号：US11509617
申请日：2006-08-25
申请人： Hiroshi Takita , Takashi Maruyama
发明人： Hiroshi Takita , Takashi Maruyama
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A layout determination method determines a layout of semiconductor devices that are to be created on a substrate by carrying out an exposure process. The layout determination method determines a number of semiconductor devices to be created on one substrate, based on exposure data of the semiconductor devices, a time limit of delivery of the semiconductor devices and a number of substrates to be used for production of the semiconductor devices, obtains coordinates of semiconductor devices arrangeable on the substrate, based on the exposure data, and determines the layout of the semiconductor devices to be created on the substrate, based on the exposure data, the number of semiconductor devices and the coordinates of the semiconductor devices.
摘要翻译：布局确定方法通过执行曝光处理来确定要在基板上创建的半导体器件的布局。布局确定方法基于半导体器件的曝光数据，半导体器件的传送时间限制和用于制造半导体器件的基板的数量来确定要在一个基板上产生的半导体器件的数量，基于曝光数据获得可布置在衬底上的半导体器件的坐标，并且基于曝光数据，半导体器件的数量和半导体器件的坐标来确定要在衬底上产生的半导体器件的布局。

3. 发明授权

US07569842B2 Method for correcting electron beam exposure data 有权
标题翻译：修正电子束曝光数据的方法
公开(公告)号：US07569842B2
公开(公告)日：2009-08-04
申请号：US11506171
申请日：2006-08-18
申请人： Hiroshi Takita
发明人： Hiroshi Takita
IPC分类号： H01J37/08 , G21K5/00 , G03C5/00 , G06F17/50
CPC分类号： B82Y40/00 , B82Y10/00 , G03F1/36 , H01J37/3026 , H01J37/3174 , H01J2237/31769
摘要： First, electron beam exposure data identifiable for each type of pattern of a semiconductor device is inputted (S601). Then, electron beam exposure data on a first type of pattern is not corrected, while electron beam exposure data on a second type of pattern is corrected (S603). The first type of pattern is, for example, a dummy pattern having no influence on the function of the semiconductor device. The second type of pattern is for example, a normal pattern having an influence on the function of the semiconductor device.
摘要翻译：首先，输入针对半导体器件的各种图案可识别的电子束曝光数据（S601）。然后，校正第一类型图案上的电子束曝光数据，而修正第二类型图案上的电子束曝光数据（S603）。第一类型的图案例如是对半导体器件的功能没有影响的虚拟图案。第二类型的图案例如是对半导体器件的功能产生影响的正常图案。

4. 发明授权

US08141009B2 Preparing data for hybrid exposure using both electron beam exposure and reticle exposure in lithographic process 有权
标题翻译：在光刻过程中使用电子束曝光和掩模版曝光准备数据进行混合曝光
公开(公告)号：US08141009B2
公开(公告)日：2012-03-20
申请号：US12398664
申请日：2009-03-05
申请人： Masaaki Miyajima , Hiromi Hoshino , Hiroshi Takita , Kozo Ogino
发明人： Masaaki Miyajima , Hiromi Hoshino , Hiroshi Takita , Kozo Ogino
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68
摘要： A method for preparing data for exposure includes forming a first plurality of rectangular patterns from a reticle preparing rule; lining an object pattern for performing reticle exposure with the first rectangular patterns, and extracting a second plurality of rectangular patterns, disposed in an N×N matrix, from the first plurality of rectangular patterns in the object pattern; and performing a violation detecting treatment and a correcting treatment of the pattern width and the pattern distance of the reticle exposure pattern on the basis of the distance between the second plurality of rectangular patterns.
摘要翻译：一种用于制备用于曝光的数据的方法包括：从掩模版准备规则形成第一多个矩形图案; 利用所述第一矩形图案衬里进行掩模版曝光的物体图案，并从所述物体图案中的所述第一多个矩形图案提取以N×N矩阵设置的第二多个矩形图案; 并且基于第二多个矩形图案之间的距离执行违反检测处理和对掩模版曝光图案的图案宽度和图案距离的校正处理。

5. 发明申请

US20090239160A1 METHOD FOR PREPARING DATA FOR EXPOSURE AND METHOD FOR MANUFACTURING PHOTO MASK 有权
标题翻译：用于制备曝光数据的方法和制造照相胶片的方法
公开(公告)号：US20090239160A1
公开(公告)日：2009-09-24
申请号：US12398664
申请日：2009-03-05
申请人： Masaaki MIYAJIMA , Hiromi Hoshino , Hiroshi Takita , Kozo Ogino
发明人： Masaaki MIYAJIMA , Hiromi Hoshino , Hiroshi Takita , Kozo Ogino
IPC分类号： G03F1/00 , G03C5/00
CPC分类号： G03F1/36 , G03F1/68
摘要： A method for preparing data for exposure includes forming a first plurality of rectangular patterns from a reticle preparing rule; lining an object pattern for performing reticle exposure with the first rectangular patterns, and extracting a second plurality of rectangular patterns, disposed in an N×N matrix, from the first plurality of rectangular patterns in the object pattern; and performing a violation detecting treatment and a correcting treatment of the pattern width and the pattern distance of the reticle exposure pattern on the basis of the distance between the second plurality of rectangular patterns.
摘要翻译：准备用于曝光的数据的方法包括从掩模版准备规则形成第一多个矩形图案; 利用所述第一矩形图案衬里进行掩模版曝光的物体图案，并从所述物体图案中的所述第一多个矩形图案提取设置在N×N矩阵中的第二多个矩形图案; 并且基于第二多个矩形图案之间的距离执行违反检测处理和对掩模版曝光图案的图案宽度和图案距离的校正处理。

6. 发明申请

US20060284120A1 Method for correcting electron beam exposure data 有权
标题翻译：修正电子束曝光数据的方法
公开(公告)号：US20060284120A1
公开(公告)日：2006-12-21
申请号：US11506171
申请日：2006-08-18
申请人： Hiroshi Takita
发明人： Hiroshi Takita
IPC分类号： G21K5/10
CPC分类号： B82Y40/00 , B82Y10/00 , G03F1/36 , H01J37/3026 , H01J37/3174 , H01J2237/31769
摘要： First, electron beam exposure data identifiable for each type of pattern of a semiconductor device is inputted (S601). Then, electron beam exposure data on a first type of pattern is not corrected, while electron beam exposure data on a second type of pattern is corrected (S603). The first type of pattern is, for example, a dummy pattern having no influence on the function of the semiconductor device. The second type of pattern is for example, a normal pattern having an influence on the function of the semiconductor device.
摘要翻译：首先，输入针对半导体器件的各种图案可识别的电子束曝光数据（S601）。然后，校正第一类型图案上的电子束曝光数据，而修正第二类型图案上的电子束曝光数据（S 603）。第一类型的图案例如是对半导体器件的功能没有影响的虚拟图案。第二类型的图案例如是对半导体器件的功能产生影响的正常图案。

7. 发明授权

US06821685B2 Block mask making method, block mask and exposure apparatus 有权
标题翻译：块掩模制作方法，掩模掩模和曝光装置
公开(公告)号：US06821685B2
公开(公告)日：2004-11-23
申请号：US10093803
申请日：2002-03-11
申请人： Hiroshi Takita , Hiromi Hoshino
发明人： Hiroshi Takita , Hiromi Hoshino
IPC分类号： G03F900
CPC分类号： G03F1/20 , H01J37/3026 , H01J2237/31762
摘要： A block mask making method is provided that can improve throughput of a process for exposing a semiconductor device having a plurality of layers. Steps S20-S22 respectively extract blocks including basic figures included in layers of IC data. For example, step S20 extracts a block from a wiring layer, and step S21extracts a block from a gate layer, step S22 extracting a block from a hole layer. In step S23, if the number of blocks extracted by steps S20-S22 is larger than the number of blocks that can be arranged on the block mask, blocks that are used frequently are selected preferentially. Step S24 determines arrangement of a block having a smaller exposure pattern closer to a center of the block mask. Data in which arrangement is fixed is output as block mask making data.
摘要翻译：提供一种块掩模制造方法，其可以提高用于暴露具有多个层的半导体器件的处理的生产量。步骤S20-S22分别提取包括IC数据层中的基本图形的块。例如，步骤S20从布线层提取块，步骤S21从栅极层提取块，步骤S22从孔层提取块。在步骤S23中，如果通过步骤S20-S22提取的块的数量大于可以在块掩码上排列的块的数量，则优先选择频繁使用的块。步骤S24确定具有更接近块掩模的中心的较小曝光图案的块的布置。输出排列固定的数据作为块掩模制作数据输出。

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