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1. 发明授权

US08484538B2 FEC (forward error correction) decoder with dynamic parameters 失效
公开(公告)号：US08484538B2
公开(公告)日：2013-07-09
申请号：US11823225
申请日：2007-06-27
申请人： Hiroshi Suzuki , Alan Y. Kwentus , Stephen Edward Krafft , Kevin M. Eddy , Steven T. Jaffe
发明人： Hiroshi Suzuki , Alan Y. Kwentus , Stephen Edward Krafft , Kevin M. Eddy , Steven T. Jaffe
IPC分类号： H03M13/35
CPC分类号： H04L1/0057 , H03M13/114 , H03M13/2927 , H03M13/2948 , H04B7/18582 , H04L1/0003 , H04L1/0009 , H04L1/0026 , H04L1/0039 , H04L1/0045 , H04L1/0065 , H04L1/0066 , H04L1/007 , H04L1/0072 , H04L1/0075
摘要： FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a signal stream to allow for adaptive changing of any 1 or more operational parameters that govern communications across a communication channel. FEC parameters are encoded directly into a data frame such that the data frame is treated identical to all other data frames within the signal stream. When the data frame actually includes FEC parameters, it is characterized as a CP (Control Packet) type. For example, when decoding an MPEG stream, an MPEG block that includes FEC parameters, that MPEG block is characterized as a CP MPEG block. The means by which FEC parameters are encoded and extracted from the signal stream allows for much easier adaptive modification of the manner by which signal are encoded, modulated, and processed within a communication system.

2. 发明授权

US07257764B2 FEC (Forward Error Correction) decoder with dynamic parameters 失效
标题翻译：具有动态参数的FEC（前向纠错）解码器
公开(公告)号：US07257764B2
公开(公告)日：2007-08-14
申请号：US10916919
申请日：2004-08-12
申请人： Hiroshi Suzuki , Alan Y. Kwentus , Stephen Edward Krafft , Kevin M. Eddy , Steven T. Jaffe
发明人： Hiroshi Suzuki , Alan Y. Kwentus , Stephen Edward Krafft , Kevin M. Eddy , Steven T. Jaffe
IPC分类号： H03M13/35
CPC分类号： H04L1/0057 , H03M13/114 , H03M13/2927 , H03M13/2948 , H04B7/18582 , H04L1/0003 , H04L1/0009 , H04L1/0026 , H04L1/0039 , H04L1/0045 , H04L1/0065 , H04L1/0066 , H04L1/007 , H04L1/0072 , H04L1/0075
摘要： FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a signal stream to allow for adaptive changing of any 1 or more operational parameters that govern communications across a communication channel. FEC parameters are encoded directly into a data frame such that the data frame is treated identical to all other data frames within the signal stream. When the data frame actually includes FEC parameters, it is characterized as a CP (Control Packet) type. For example, when decoding an MPEG stream, an MPEG block that includes FEC parameters, that MPEG block is characterized as a CP MPEG block. The means by which FEC parameters are encoded and extracted from the signal stream allows for much easier adaptive modification of the manner by which signal are encoded, modulated, and processed within a communication system.
摘要翻译：具有动态参数的FEC（前向纠错）解码器。 FEC参数可以被编码到信号流中并随后从信号流中提取的新颖手段，以允许对通过通信信道进行通信的任何一个或多个操作参数进行自适应改变。 FEC参数被直接编码到数据帧中，使得数据帧被视为与信号流内的所有其他数据帧相同。当数据帧实际上包含FEC参数时，它被表征为CP（控制分组）类型。例如，当解码MPEG流时，包括FEC参数的MPEG块，该MPEG块被表征为CP MPEG块。从信号流中对FEC参数进行编码和提取的手段允许在通信系统内对信号进行编码，调制和处理的方式进行更容易的自适应修改。

3. 发明授权

US08014449B2 Communications signal transcoder 有权
标题翻译：通信信号转码器
公开(公告)号：US08014449B2
公开(公告)日：2011-09-06
申请号：US12825893
申请日：2010-06-29
申请人： Alan Y. Kwentus , Charles Alan Brooks , Steven T. Jaffe , Stephen Edward Krafft
发明人： Alan Y. Kwentus , Charles Alan Brooks , Steven T. Jaffe , Stephen Edward Krafft
IPC分类号： H04N7/12
CPC分类号： H04N21/2383 , H04N21/4382
摘要： Communications signal transcoder. A solution is provided to transcode a signal from a first signal type to a second signal type to ensure proper interfacing between devices that may operate using different signal types. For example, within a communication system, a first signal type (having a first modulation type, e.g., 8 PSK) may be received. The transcoder then ensures that this signal, after it has undergone any initial processing (such as tuning, down-converting, decoding, and so on), is encoded into a second signal type (having a second modulation type, e.g., QPSK) such that it can interface properly with a device for which the received signal is intended. This transcoder functionality may be implemented within discrete components, or it may alternatively be integrated within a functional block of an integrated circuit. This functionality may be implemented in a variety of communication systems including satellite, cable television, Internet, and others.
摘要翻译：通信信号转码器。提供了将信号从第一信号类型转换为第二信号类型的解决方案，以确保可以使用不同信号类型操作的设备之间的适当接口。例如，在通信系统中，可以接收第一信号类型（具有第一调制类型，例如8PSK）。代码转换器然后确保该信号经过任何初始处理（诸如调谐，下变换，解码等等）之后被编码为第二信号类型（具有第二调制类型，例如QPSK），例如它可以与接收到的信号的设备正确连接。该代码转换器功能可以在分立组件内实现，或者可选地集成在集成电路的功能块内。该功能可以在包括卫星，有线电视，因特网等的各种通信系统中实现。

4. 发明授权

US07596189B2 Quadrature receiver sampling architecture 有权
标题翻译：正交接收机采样架构
公开(公告)号：US07596189B2
公开(公告)日：2009-09-29
申请号：US11593273
申请日：2006-11-06
申请人： Tommy Yu , Steven T. Jaffe , Stephen Edward Krafft
发明人： Tommy Yu , Steven T. Jaffe , Stephen Edward Krafft
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L27/00
摘要： Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.
摘要翻译：正交接收机采样架构。信号ADC为I和Q流执行模数转换。模拟MUX在适当的时间选择适当的I和Q基带模拟输入流输入ADC。还可以采用数字滤波器来补偿在I和Q信道的样本之间的任何引入的延迟，当寻求恢复已被发送到使用该正交接收器架构和/或信号处理的通信接收机的符号时。在一个实施例中，如果ADC以基本上是I和Q通道的采样率的两倍的速率被计时，则在ADC的输出处的数字I和数字Q数据之间将存在二分之一采样时钟延迟。然后在解调器处理输入信号之前去除该延迟以恢复发送的符号。

5. 发明授权

US08520756B2 PHY sub-channel processing 有权
公开(公告)号：US08520756B2
公开(公告)日：2013-08-27
申请号：US13591389
申请日：2012-08-22
申请人： Steven T. Jaffe , Stephen Edward Krafft
发明人： Steven T. Jaffe , Stephen Edward Krafft
IPC分类号： H04L27/28
CPC分类号： H04L1/0072 , H04L1/0041 , H04L2001/0097
摘要： Physical layer (PHY) sub-channel processing. A soft symbol decision stream is arranged into a number of sub-channels to reduce substantially the processing performed within a communication receiver on data that is not intended for that communication receiver. In other embodiments, a predetermined approach is employed to arrange the soft symbol decision stream into one or more frames; each frame may have one or more soft symbol blocks; and each soft symbol block may have one or more symbols. Each of the soft symbol blocks, within a frame, may be assigned to a sub-channel. Only the soft symbol blocks that contain information destined for the communication receiver need be decoded. Only the sub-channel that includes these soft symbol blocks, destined for this communication receiver, need be decoded. The soft symbol blocks not within the sub-channel may be discarded thereby recovering some of the processing capabilities of the communication receiver.

6. 发明申请

US20120235841A1 DIGITAL CORRECTION TECHNIQUES FOR DATA CONVERTERS 有权
标题翻译：数据转换器的数字校正技术
公开(公告)号：US20120235841A1
公开(公告)日：2012-09-20
申请号：US13228301
申请日：2011-09-08
申请人： Ramon Alejandro Gomez , Loke Kun Tan , Bruce J. Currivan , Steven T. Jaffe , Thomas Joseph Kolze , Lin He
发明人： Ramon Alejandro Gomez , Loke Kun Tan , Bruce J. Currivan , Steven T. Jaffe , Thomas Joseph Kolze , Lin He
IPC分类号： H03M1/06
CPC分类号： H03M1/06 , H03M1/00 , H03M1/0695 , H03M1/1061 , H03M1/12 , H03M1/1215
摘要： A method and apparatus is disclosed to compensate for impairments within a data converter such that its output is a more accurate representation of its input. The data converter includes a main data converter, a reference data converter, and a correction module. The main data converter may be characterized as having the impairments. As a result, the output of the main data converter is not the most accurate representation of its input. The reference data converter is designed such that the impairments are not present. The correction module estimates the impairments present within the main data converter using its output and the reference data converter to generate corrections coefficients. The correction module adjusts the output of the main data converter using the corrections coefficients to improve the performance of the data converter.
摘要翻译：公开了一种用于补偿数据转换器内的损伤的方法和装置，使得其输出是其输入的更准确的表示。数据转换器包括主数据转换器，参考数据转换器和校正模块。主数据转换器可以被表征为具有损伤。因此，主数据转换器的输出不是其输入的最准确的表示。参考数据转换器被设计成不存在损伤。校正模块使用其输出和参考数据转换器来估计存在于主数据转换器内的损伤以产生校正系数。校正模块使用校正系数调整主数据转换器的输出，以提高数据转换器的性能。

7. 发明授权

US07961255B2 Television functionality on a chip 有权
标题翻译：芯片上的电视功能
公开(公告)号：US07961255B2
公开(公告)日：2011-06-14
申请号：US12367425
申请日：2009-02-06
申请人： David A. Baer , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian F. Schoner , Chengfuh Jeffrey Tang , Chuck Monahan , Darren D. Neuman , David Chao Hua Wu , Francis Cheung , Greg A. Kranawetter , Hoang Nhu , Hsien-Chih Jim Tseng , Iue-Shuenn Chen , James D. Sweet , Jeffrey S. Bauch , Keith LaRell Klinger , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Van Tran , Shawn V. Johnson , Steven T. Jaffe , Thu T. Nguyen , Ut Nguyen , Yao-Hua Steven Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy C. Denk
发明人： David A. Baer , Jeff Tingley , Aleksandr Movshovich , Brad Grossman , Brian F. Schoner , Chengfuh Jeffrey Tang , Chuck Monahan , Darren D. Neuman , David Chao Hua Wu , Francis Cheung , Greg A. Kranawetter , Hoang Nhu , Hsien-Chih Jim Tseng , Iue-Shuenn Chen , James D. Sweet , Jeffrey S. Bauch , Keith LaRell Klinger , Patrick Law , Rajesh Mamidwar , Dan Simon , Sang Van Tran , Shawn V. Johnson , Steven T. Jaffe , Thu T. Nguyen , Ut Nguyen , Yao-Hua Steven Tseng , Brad Delanghe , Ben Giese , Jason Demas , Lakshman Ramakrishnan , Sandeep Bhatia , Guang-Ting Shih , Tracy C. Denk
IPC分类号： H04N5/44 , H04N3/27
CPC分类号： H04N21/426 , H04N5/4401 , H04N5/44504 , H04N5/46 , H04N7/035 , H04N21/4263 , H04N21/4305 , H04N2005/91364
摘要： A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.
摘要翻译：公开了一种提供用于在单个集成电路芯片上提供电视功能的成本有效方法的芯片上的电视（TVOC）系统。 TVOC包括以各种输入和输出格式接收和显示电视信号所必需的功能。 TVOC可用于有线和卫星电视的机顶盒，或直接在电视机内使用。所提供的所有功能可以在单个集成电路上提供。 TVOC包括数据传输模块，IF解调器，数字音频引擎，模拟音频引擎，数字视频引擎和模拟视频引擎。 TVOC还包括三套接口，包括输出接口，控制接口和辅助接口。其他特征和实施例提供增强的功能和提高的效率。

8. 发明申请

US20090122925A1 Viterbi slicer for turbo codes 有权
标题翻译：涡轮代码维特比切片机
公开(公告)号：US20090122925A1
公开(公告)日：2009-05-14
申请号：US12358362
申请日：2009-01-23
申请人： Steven T. Jaffe , Kelly B. Cameron , Christopher R. Jones
发明人： Steven T. Jaffe , Kelly B. Cameron , Christopher R. Jones
IPC分类号： H04L27/06
CPC分类号： H04L1/0066 , H04L1/005 , H04L1/0054 , H04L2027/0028 , H04L2027/0055
摘要： A method for synchronizing receivers that receive turbo encoded signals to a received signal. Turbo encoding may enable signals to be decoded at a much lower signal to noise ratio than previously practical. A traditional method of synchronizing a receiver to an incoming signal is to use a slicer to determine a received symbol and then to compare the determined symbol to the incoming waveform, in order to adjust the phase of the slicer with respect to the incoming signal. At signal low levels, at which turbo encoded signals may be decoded, this slicing method may be prone to errors that may disrupt the synchronization of the receiver to the incoming signal. By replacing the slicer by a Viterbi decoder with zero traceback (i.e., one which does not consider future values of the signal only past values) a prediction as to what the incoming signal is can be made. Because the Viterbi decoder can consider past signal values it can predict the present symbol being received with higher reliability than by using a slicer, which considers only the present value of the incoming signal.
摘要翻译：一种用于将接收turbo编码信号的接收机同步到接收信号的方法。 Turbo编码可以使信号以比以前实际的低得多的信噪比进行解码。将接收机同步到传入信号的传统方法是使用限幅器来确定接收到的符号，然后将确定的符号与输入波形进行比较，以便相对于输入信号调节限幅器的相位。在信号低电平处，可以对Turbo编码信号进行解码，该分片方法可能容易出现可能中断接收机与输入信号的同步的错误。通过用零回溯的维特比解码器（即，不将信号的未来值仅仅考虑过去的值）来替换限幅器，可以对可以进行什么输入信号进行预测。因为维特比解码器可以考虑过去的信号值，所以它可以比使用仅考虑输入信号的当前值的限幅器更可靠地预测接收到的当前码元。

9. 发明授权

US07027528B2 Timing recovery using the pilot signal in high definition TV 有权
标题翻译：使用高分辨率电视中的导频信号进行定时恢复
公开(公告)号：US07027528B2
公开(公告)日：2006-04-11
申请号：US10895579
申请日：2004-07-21
申请人： Tian-Min Liu , Loke Kun Tan , Steven T. Jaffe
发明人： Tian-Min Liu , Loke Kun Tan , Steven T. Jaffe
IPC分类号： H04L27/14
CPC分类号： H04N5/21 , H04B1/68 , H04L25/03057 , H04L27/02 , H04L27/066 , H04L27/2273 , H04L27/3427 , H04L27/3827 , H04L2025/03382 , H04L2025/0342 , H04L2025/0349 , H04L2025/03503 , H04L2027/0032 , H04L2027/0042 , H04L2027/0057 , H04L2027/0067 , H04L2027/0087 , H04N5/211 , H04N5/44 , H04N5/4401 , H04N5/455 , H04N5/46 , H04N11/002
摘要： Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fc=fS/4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fS is correct, and will be shifted in one direction or the other if the sampling frequency fS is too high or too low.
摘要翻译：公开了适用于双模QAM / VSB接收机系统的改进的载波恢复和符号定时系统和方法。载波和符号定时采集和跟踪环路被相位/频率锁定到在给定频率下在输入VSB频谱中提供的插入导频信号。输入频谱以基带为中心，并且通过等效滤波器提取导频，该等效滤波器用作具有以导频频率为中心的通带的带通滤波器。由于给出了导频信号的频率，所以在频域中对于任何采样频率的位置是确定性的。提供了接收机的采样频率，使得该关系被表示为f / c = f S / S / 4。当通过锁相环路进行跟踪时，如果采样频率f S S S正确，则导频信号将出现在频谱中的正确位置，并且如果采样频率f S S太高或太低。

10. 发明授权

US06775334B1 Equalization and decision-directed loops with trellis demodulation in high definition TV 有权
公开(公告)号：US06775334B1
公开(公告)日：2004-08-10
申请号：US09433733
申请日：1999-11-03
申请人： Tian-Min Liu , Loke Kun Tan , Steven T. Jaffe
发明人： Tian-Min Liu , Loke Kun Tan , Steven T. Jaffe
IPC分类号： H03D100
CPC分类号： H04L27/3827 , H04B1/68 , H04L25/03057 , H04L27/02 , H04L27/066 , H04L27/2273 , H04L27/3427 , H04L2025/03382 , H04L2025/0342 , H04L2025/0349 , H04L2025/03503 , H04L2027/0032 , H04L2027/0042 , H04L2027/0057 , H04L2027/0067 , H04L2027/0087 , H04N5/21 , H04N5/211 , H04N5/44 , H04N5/4401 , H04N5/46 , H04N11/002
摘要： Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE's ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

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