会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Semiconductor memory having a barrier transistor between a bit line and
a sensing amplifier
    • 具有在位线和感测放大器之间的势垒晶体管的半导体存储器
    • US4794569A
    • 1988-12-27
    • US863190
    • 1986-05-14
    • Hiroshi SaharaHaruki TodaShigeo Ohshima
    • Hiroshi SaharaHaruki TodaShigeo Ohshima
    • G11C11/409G11C11/4094G11C11/4096G11C7/00
    • G11C11/4096G11C11/4094
    • In this invention, in a sensing circuit of a dynamic memory, barrier transistors are provided between the bit lines and the sensing amplifier. A circuit is provided that, on sensing and on data transfer, changes the gate potential of the barrier transistors so that during the sensing operation the barrier transistors are temporarily turned OFF, so that sensing can be carried out with high sensitivity, as the sensing system is not affected by the parasitic capacitance of the bit lines, while, on data transfer to the input/output lines, the gate potential of the barrier transistors is raised to a level greater than a value reached by adding the threshold value of the MOS transistors to the power source voltage, so that the conductance of the barrier transistors is increased, thereby speeding up the presensing of the input/output lines in the sensing circuit.
    • 在本发明中,在动态存储器的感测电路中,在位线和感测放大器之间设置有阻挡晶体管。 提供了一种电路,其在感测和数据传输时改变势垒晶体管的栅极电位,使得在感测操作期间,阻挡晶体管暂时断开,使得可以以高灵敏度进行感测,作为感测系统 不受位线的寄生电容的影响,而在向输入/输出线路传输数据时,势垒晶体管的栅极电位升高到大于通过将MOS晶体管的阈值相加而达到的值 以使得阻挡晶体管的电导增加,从而加速感测电路中的输入/输出线的预置。
    • 5. 发明授权
    • Semiconductor memory system
    • 半导体存储系统
    • US5107464A
    • 1992-04-21
    • US480902
    • 1990-02-16
    • Hiroshi SaharaHaruki TodaShigeo Ohshima
    • Hiroshi SaharaHaruki TodaShigeo Ohshima
    • G11C11/401G11C29/00G11C29/04
    • G11C29/846
    • In a semiconductor memory system of the serial column access type, a redundant column is used for replacing a defective column. Redundant data lines are connected to the redundant column through a redundant column selection gate. A defective address detection circuit detects the address of a defective column to enable the redundant column selection gate. An address counter is provided for a defective address detection circuit. A redundant column selection circuit selects the redundant column in response to a detection signal from the defective address detection circuit. A data line switching circuit switches, in redundant column select mode, the data lines connecting to a data input/output drive circuit from said regular data lines to the redundant data lines. With this circuit arrangement, in a redundant column select mode, the regular data lines are separated from the data input/output drive circuit. Therefore, even if a shift register constituting a regular column selection circuit operates and the defective column selection gate is enabled to set up a connection of the defective column to the regular data lines, the error data from the defective column is never output. Further, the shift register is operable irrespective of the defective column detection.
    • 7. 发明授权
    • Flip-flop circuit
    • 触发电路
    • US4678934A
    • 1987-07-07
    • US884629
    • 1986-07-11
    • Koichi MagomeHaruki TodaHiroyuki KoinumaHiroshi SaharaKiminobu SuzukiShigeo OhshimaKenji Komatsu
    • Koichi MagomeHaruki TodaHiroyuki KoinumaHiroshi SaharaKiminobu SuzukiShigeo OhshimaKenji Komatsu
    • G11C11/40G11C8/06H03K3/356H03K3/26G11C7/00H03K17/687H03K19/094
    • H03K3/356026G11C8/06
    • A flip-flop circuit has a power terminal set at 5 V, first and second output terminals, a latch section for charging one of the first and second terminals to 5 V and discharging the other one of the first and second terminals to 0 V in accordance with an input signal, a first MOS transistor having a current path connected between the power and first output terminals, a second MOS transistor for charging the gate of the first MOS transistor while the potential of the second output terminal is changed from 5 V to 0 V, and a capacitor for bootstrapping the gate potential of the first MOS transistor to turn on the first MOS transistor. The flip-flop circuit further includes a third MOS transistor, having a current path connected between the gate of the first MOS transistor and the first output terminal and a gate connected to the first output terminal, for charging the gate of the first MOS transistor when the gate potential of the first MOS transistor is dropped a predetermined level in comparison with that of the first output terminal.
    • 触发器电路具有设置在5V的电源端子,第一和第二输出端子,用于将第一和第二端子中的一个充电至5V并将第一和第二端子中的另一个放电至0V的锁存部分 根据输入信号,具有连接在电源和第一输出端子之间的电流路径的第一MOS晶体管,第二MOS晶体管,用于对第一MOS晶体管的栅极充电,同时第二输出端子的电位从5V变为 0V,以及用于自举第一MOS晶体管的栅极电位以使第一MOS晶体管导通的电容器。 触发器电路还包括第三MOS晶体管,其具有连接在第一MOS晶体管的栅极和第一输出端子之间的电流路径和连接到第一输出端子的栅极,用于对第一MOS晶体管的栅极充电, 与第一输出端子相比,第一MOS晶体管的栅极电位下降到预定水平。
    • 9. 发明授权
    • Operation mode setting circuit for dram
    • 操作模式设定电路
    • US4984216A
    • 1991-01-08
    • US307701
    • 1989-02-08
    • Haruki TodaShigeo OhshimaTatsuo Ikawa
    • Haruki TodaShigeo OhshimaTatsuo Ikawa
    • G11C11/401G11C7/10G11C11/406G11C11/4076
    • G11C11/406G11C11/4076G11C7/1045
    • A signal externally supplied to determine the operation mode is supplied to a first buffer circuit. A CAS signal is supplied to a second buffer circuit. The signals whose levels are converted by the first and second buffer circuits are supplied to a mode selection circuit. The operation of the mode selection circuit is controlled by a RAS signal, and it latches and outputs a mode selection signal based on the outputs of the first and second buffer circuits. An externally supplied address signal and an address signal formed in the device are supplied to address buffer circuit. The address buffer circuit selects one of the received address signals based on the RAS signal anad the mode selection signal output from the mode selection circuit. A selected one of the address signals is supplied to a word line selection/driving circuit. When a mode other than the auto-refresh mode is specified, the mode setting signal is set up before the RAS signal is activated. The set-up allowance time with respect to the activation timing of the RAS signal is set to be larger than the minimum value of the set-up allowance time of the external address signal. The mode setting signal is latched by the mode selection circuit when the RAS signal is activated. The latched signal is used to select and control the operation mode.