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1. 发明申请

US20080320331A1 CONTROL APPARATUS 有权
标题翻译：控制装置
公开(公告)号：US20080320331A1
公开(公告)日：2008-12-25
申请号：US12141365
申请日：2008-06-18
申请人： Hiroshi Nakatani , Yoshito Sameda , Akira Sawada , Jun Takehara , Kouichi Takene , Hiroyuki Nishikawa
发明人： Hiroshi Nakatani , Yoshito Sameda , Akira Sawada , Jun Takehara , Kouichi Takene , Hiroyuki Nishikawa
IPC分类号： G06F11/263
CPC分类号： G01R31/318555 , G01R31/318572 , G06F11/2236
摘要： For a control apparatus to be boundary scan testable even when running, including processor cores in an operator to be capable of self-repairing a troubling part, an operator (2) has processor cores (2a, 2b) connected to a boundary scan bus (12), and adapted to mutually diagnose opponent processor cores for troubles, by boundary scan testing each other in a time-dividing manner.
摘要翻译：对于即使在运行时即使在操作者中能够自我修复麻烦部分的处理器核心的边界扫描测试的控制装置，操作者（2）具有连接到边界扫描总线的处理器核心（2a，2b） 12），并且通过以时分方式进行边界扫描测试来适应于相互诊断对方处理器核心的麻烦。

2. 发明授权

US07870429B2 Control apparatus 有权
标题翻译：控制装置
公开(公告)号：US07870429B2
公开(公告)日：2011-01-11
申请号：US12141365
申请日：2008-06-18
申请人： Hiroshi Nakatani , Yoshito Sameda , Akira Sawada , Jun Takehara , Kouichi Takene , Hiroyuki Nishikawa
发明人： Hiroshi Nakatani , Yoshito Sameda , Akira Sawada , Jun Takehara , Kouichi Takene , Hiroyuki Nishikawa
IPC分类号： G06F11/00
CPC分类号： G01R31/318555 , G01R31/318572 , G06F11/2236
摘要： For a control apparatus to be boundary scan testable even when running, including processor cores in an operator to be capable of self-repairing a troubling part, an operator (2) has processor cores (2a, 2b) connected to a boundary scan bus (12), and adapted to mutually diagnose opponent processor cores for troubles, by boundary scan testing each other in a time-dividing manner.
摘要翻译：对于即使在运行时即使在操作者中能够自我修复麻烦部分的处理器核心的边界扫描测试的控制装置，操作者（2）具有连接到边界扫描总线的处理器核心（2a，2b） 12），并且通过以时分方式进行边界扫描测试来适应于相互诊断对方处理器核心的麻烦。

3. 发明申请

US20080281896A1 INDUSTRIAL CONTROLLER 有权
标题翻译：工业控制器
公开(公告)号：US20080281896A1
公开(公告)日：2008-11-13
申请号：US12108774
申请日：2008-04-24
申请人： Yoshito SAMEDA , Hiroshi Nakatani , Akira Sawada , Jun Takehara , Hiroyuki Nishikawa , Motohiko Okabe
发明人： Yoshito SAMEDA , Hiroshi Nakatani , Akira Sawada , Jun Takehara , Hiroyuki Nishikawa , Motohiko Okabe
IPC分类号： G06F7/48
CPC分类号： H04L9/008 , G06F11/085
摘要： A first arithmetic operator (11) includes a first modular arithmetic coding encoder (11b) for encoding a numeric data transmitted by a command from a central controller (31) into a modular arithmetic code, a first arithmetic operation processor (11a) using the numeric data as modular arithmetic coded as an input operand, for executing an arithmetic operation based on a command from the central controller (13), to provide an output in the form of a modular arithmetic code, and a first modular arithmetic code decoder (11c) for determining presence or absence of a bit error in the numeric data output from the first arithmetic operation processor, correcting the bit error, if detected any, to output a decoded numeric data.
摘要翻译：第一算术运算器（11）包括：第一模数算术编码编码器（11b），用于将通过中央控制器（31）的命令发送的数值数据编码为模数运算代码;第一算术运算处理器（11a），使用将作为输入操作数编码的模数算术的数值数据作为基于来自中央控制器（13）的命令执行算术运算，提供模数运算代码形式的输出和第一模运算代码解码器（ 11c）用于确定从第一算术运算处理器输出的数值数据中存在或不存在位错误，如果检测到的话，校正位错误，以输出解码的数字数据。

4. 发明授权

US08224882B2 Industrial controller 有权
标题翻译：工业控制器
公开(公告)号：US08224882B2
公开(公告)日：2012-07-17
申请号：US12108774
申请日：2008-04-24
申请人： Yoshito Sameda , Hiroshi Nakatani , Akira Sawada , Jun Takehara , Hiroyuki Nishikawa , Motohiko Okabe
发明人： Yoshito Sameda , Hiroshi Nakatani , Akira Sawada , Jun Takehara , Hiroyuki Nishikawa , Motohiko Okabe
IPC分类号： G06F7/38
CPC分类号： H04L9/008 , G06F11/085
摘要： A first arithmetic operator (11) includes a first modular arithmetic coding encoder (11b) for encoding a numeric data transmitted by a command from a central controller (31) into a modular arithmetic code, a first arithmetic operation processor (11a) using the numeric data as modular arithmetic coded as an input operand, for executing an arithmetic operation based on a command from the central controller (13), to provide an output in the form of a modular arithmetic code, and a first modular arithmetic code decoder (11c) for determining presence or absence of a bit error in the numeric data output from the first arithmetic operation processor, correcting the bit error, if detected any, to output a decoded numeric data.
摘要翻译：第一算术运算器（11）包括：第一模数算术编码编码器（11b），用于将通过中央控制器（31）的命令发送的数值数据编码为模数运算代码;第一算术运算处理器（11a）数据作为编码为输入操作数的模数运算，用于基于来自中央控制器（13）的命令执行算术运算，以提供模运算代码形式的输出和第一模运算代码解码器（11c）用于确定从第一算术运算处理器输出的数值数据中存在或不存在位错误，如果检测到的话，校正位错误，以输出解码的数字数据。

5. 发明申请

US20130082739A1 CLOCK DIAGNOSIS CIRCUIT 失效
标题翻译：时钟诊断电路
公开(公告)号：US20130082739A1
公开(公告)日：2013-04-04
申请号：US13614235
申请日：2012-09-13
申请人： Naoya OHNISHI , Hiroshi Nakatani , Yoshito Sameda , Jun Takehara , Makoto Toko
发明人： Naoya OHNISHI , Hiroshi Nakatani , Yoshito Sameda , Jun Takehara , Makoto Toko
IPC分类号： G01R29/02
CPC分类号： H03K5/19 , G06F1/04
摘要： A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.
摘要翻译：时钟诊断电路包括：将时钟延迟规定时间的延迟电路，该规定时间不大于时钟脉冲宽度; 整数乘法延迟电路，用于将从延迟电路输出的延迟时钟延迟预定数量的周期; 使用延迟时钟对时钟进行编码的第一异或电路; 使用积分乘法延迟电路的输出来对第一异或电路的输出进行解码的第二异或电路; 以及比较电路，用于将时钟与第二异或电路的输出进行比较，从而检测时钟的故障。

6. 发明授权

US08717066B2 Clock diagnosis circuit 失效
标题翻译：时钟诊断电路
公开(公告)号：US08717066B2
公开(公告)日：2014-05-06
申请号：US13614235
申请日：2012-09-13
申请人： Naoya Ohnishi , Hiroshi Nakatani , Yoshito Sameda , Jun Takehara , Makoto Toko
发明人： Naoya Ohnishi , Hiroshi Nakatani , Yoshito Sameda , Jun Takehara , Makoto Toko
IPC分类号： H03K5/22
CPC分类号： H03K5/19 , G06F1/04
摘要： A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock.
摘要翻译：时钟诊断电路包括：将时钟延迟规定时间的延迟电路，该规定时间不大于时钟脉冲宽度; 整数乘法延迟电路，用于将从延迟电路输出的延迟时钟延迟预定数量的周期; 使用延迟时钟对时钟进行编码的第一异或电路; 使用积分乘法延迟电路的输出来对第一异或电路的输出进行解码的第二异或电路; 以及比较电路，用于将时钟与第二异或电路的输出进行比较，从而检测时钟的故障。

7. 发明授权

US08131900B2 Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line 有权
标题翻译：总线信号控制电路，用于使用单独的总线诊断线检测总线信号异常
公开(公告)号：US08131900B2
公开(公告)日：2012-03-06
申请号：US12432896
申请日：2009-04-30
申请人： Jun Takehara , Naruhiko Aramaki , Toshikazu Kawamura , Yoshito Sameda , Hiroshi Nakatani , Motohiko Okabe , Yukitaka Yoshida
发明人： Jun Takehara , Naruhiko Aramaki , Toshikazu Kawamura , Yoshito Sameda , Hiroshi Nakatani , Motohiko Okabe , Yukitaka Yoshida
IPC分类号： G06F13/00 , H04L1/14
CPC分类号： G06F11/0793 , G06F11/0745
摘要： A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.
摘要翻译：存储器控制单元根据来自主设备的指令控制对从设备的数据的写入和读取。总线诊断线从总线信号控制电路直接连接到从设备的总线信号接收终端，而不通过地址总线和控制信号线。总线信号异常处理单元将从总线信号控制电路输出的输出总线信号与地址总线和控制信号线进行比较，其中反馈总线信号通过总线诊断线反馈，以确定差异的存在/不存在。当在总线信号异常处理单元中确定存在差异时，存储器控制单元延长正在执行的总线周期的总线周期。

8. 发明申请

US20120185858A1 PROCESSOR OPERATION MONITORING SYSTEM AND MONITORING METHOD THEREOF 审中-公开
标题翻译：处理器操作监控系统及其监控方法
公开(公告)号：US20120185858A1
公开(公告)日：2012-07-19
申请号：US13349710
申请日：2012-01-13
申请人： Naoya OHNISHI , Hiroshi Nakatani , Yoshito Sameda , Jun Takehara , Atsushi Inoue , Makoto Toko
发明人： Naoya OHNISHI , Hiroshi Nakatani , Yoshito Sameda , Jun Takehara , Atsushi Inoue , Makoto Toko
IPC分类号： G06F9/46
CPC分类号： G06F11/0715 , G06F11/0721 , G06F11/076 , G06F11/20
摘要： A processor includes a computation unit; a storage unit storing a program; and a data transmission circuit that transmits to an operation monitoring unit a signal corresponding to an instruction for reporting the execution stage of the program. The operation monitoring unit: includes a transition operation identification. circuit and a loop processing identification circuit. The transition operation identification circuit receives a start ID instruction with an attached ID that identifies a task; a termination ID instruction that identifies termination of task operation; and if the task is execution of loop processing, a loop instruction that reports the maximum value of the number of times of this loop processing. The transition operation identification circuit identifies success of the transition operations of the tasks of the program, based on the ID instructions. The loop processing identification circuit identifies abnormality of the number of times of loop processing.
摘要翻译：处理器包括计算单元; 存储单元，存储程序; 以及数据传输电路，向操作监视单元发送与用于报告程序的执行阶段的指令相对应的信号。操作监视单元包括过渡操作标识。电路和环路处理识别电路。转移操作识别电路接收具有识别任务的附加ID的开始ID指令; 终止ID指令，用于标识任务操作的终止; 并且如果任务是执行循环处理，则循环指令报告该循环处理的次数的最大值。过渡操作识别电路基于ID指令来识别程序的任务的转换操作的成功。循环处理识别电路识别循环处理次数的异常。

9. 发明申请

US20090287867A1 BUS SIGNAL CONTROL CIRCUIT AND SIGNAL PROCESSING CIRCUIT HAVING BUS SIGNAL CONTROL CIRCUIT 有权
标题翻译：具有总线信号控制电路的总线信号控制电路和信号处理电路
公开(公告)号：US20090287867A1
公开(公告)日：2009-11-19
申请号：US12432896
申请日：2009-04-30
申请人： Jun Takehara , Naruhiko Aramaki , Toshikazu Kawamura , Yoshito Sameda , Hiroshi Nakatani , Motohiko Okabe , Yukitaka Yoshida
发明人： Jun Takehara , Naruhiko Aramaki , Toshikazu Kawamura , Yoshito Sameda , Hiroshi Nakatani , Motohiko Okabe , Yukitaka Yoshida
IPC分类号： G06F13/40
CPC分类号： G06F11/0793 , G06F11/0745
摘要： A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.
摘要翻译：存储器控制单元根据来自主设备的指令控制对从设备的数据的写入和读取。总线诊断线从总线信号控制电路直接连接到从设备的总线信号接收终端，而不通过地址总线和控制信号线。总线信号异常处理单元将从总线信号控制电路输出的输出总线信号与地址总线和控制信号线进行比较，其中反馈总线信号通过总线诊断线反馈，以确定差异的存在/不存在。当在总线信号异常处理单元中确定存在差异时，存储器控制单元延长正在执行的总线周期的总线周期。

10. 发明申请

US20070147232A1 REDUNDANT SUPERVISORY CONTROL SYSTEM, AND REDUNDANCY SWITCHING METHOD OF THE SAME 有权
标题翻译：冗余监控系统及其冗余切换方法
公开(公告)号：US20070147232A1
公开(公告)日：2007-06-28
申请号：US11566310
申请日：2006-12-04
申请人： Jun Takehara , Akira Sawada , Makoto Toko , Hiroyuki Kusakabe , Shinya Kono , Yuuji Umeda
发明人： Jun Takehara , Akira Sawada , Makoto Toko , Hiroyuki Kusakabe , Shinya Kono , Yuuji Umeda
IPC分类号： H04L12/26 , H04J3/14
CPC分类号： G05B9/02
摘要： An object is to provide a redundant supervisory control system and a redundancy switching method thereof. In the redundant supervisory control system, remote I/O apparatuses are less likely to be inaccessible, even in a case where failures occur in plural locations. Thus, the reliability of the system is enhanced. The redundant supervisory control system including a plurality of first loop interface units in each of a pair of controllers, second loop interface units, and communication cables each connecting the plurality of first and second loop interface units with one another in a circular loop. The redundant supervisory control system is configured by connecting the controllers and the remote I/O units to one another in a plurality of loop networks. In a case where abnormality in the loop networks is detected by use of received data in the networks, the first and second loop interface units that can perform normal reception are automatically selected.
摘要翻译：目的在于提供一种冗余监控系统及其冗余切换方法。在冗余监控系统中，即使在多个位置发生故障的情况下，远程I / O设备也不太可能无法访问。因此，提高了系统的可靠性。冗余监控系统包括在一对控制器，第二回路接口单元和通信电缆中的每一个中的多个第一回路接口单元，每个控制器，第二回路接口单元和通信电缆中的每一个以圆形回路相互连接多个第一和第二回路接口单元。冗余监控系统通过在多个环路网络中将控制器和远程I / O单元彼此连接来配置。在通过使用网络中的接收数据检测到环路网络中的异常的情况下，可以自动选择能够执行正常接收的第一和第二环路接口单元。

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