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1. 发明申请

US20070205467A1 semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070205467A1
公开(公告)日：2007-09-06
申请号：US11649269
申请日：2007-01-04
申请人： Hiroshi Morioka , Jusuke Ogura , Sergey Pidin
发明人： Hiroshi Morioka , Jusuke Ogura , Sergey Pidin
IPC分类号： H01L29/76
CPC分类号： H01L21/76877 , H01L21/823807 , H01L21/823864 , H01L21/823871 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.
摘要翻译：提供具有接触结构的半导体器件。半导体器件包括：导电区域; 形成在所述导电区域上以实现层的第一膜和第二膜; 以及接触电极，该接触电极通过该层延伸到导电区域，并且形成为用该接触电极的一部分来代替该层的一部分，其中该部分仅由第一膜构成，只有第二膜或第一膜的一部分和第二膜的一部分两者，并且第一膜的部分占该层的该部分的主要部分。

2. 发明授权

US08749062B2 Semiconductor device and process for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08749062B2
公开(公告)日：2014-06-10
申请号：US11649269
申请日：2007-01-04
申请人： Hiroshi Morioka , Jusuke Ogura , Sergey Pidin
发明人： Hiroshi Morioka , Jusuke Ogura , Sergey Pidin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/76877 , H01L21/823807 , H01L21/823864 , H01L21/823871 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer.
摘要翻译：提供具有接触结构的半导体器件。半导体器件包括：导电区域; 形成在所述导电区域上以实现层的第一膜和第二膜; 以及接触电极，该接触电极通过该层延伸到导电区域，并且形成为用该接触电极的一部分来代替该层的一部分，其中该部分仅由第一膜构成，只有第二膜或第一膜的一部分和第二膜的一部分两者，并且第一膜的部分占该层的该部分的主要部分。

3. 发明申请

US20080124856A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080124856A1
公开(公告)日：2008-05-29
申请号：US11639344
申请日：2006-12-15
申请人： Sergey Pidin , Tamotsu Owada
发明人： Sergey Pidin , Tamotsu Owada
IPC分类号： H01L21/71 , H01L21/04
CPC分类号： H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A method of manufacturing a semiconductor device, in which a stress film having a large stress can be formed with high accuracy over a transistor. The method comprises the steps of: depositing a tensile stress film over the whole surface of a substrate having formed thereon an n-MOSFET; removing by etching the deposited stress film while leaving it on the n-MOSFET; and performing UV irradiation to the remaining stress film. By the UV irradiation, a tensile stress of the stress film is improved. Further, although the stress film is cured by the UV irradiation, occurrence of etching defects caused by the curing is prevented because the UV irradiation is performed after the etching. Thus, speeding-up and high quality of the n-MOSFET can be attained.
摘要翻译：一种制造半导体器件的方法，其中可以以高精度在晶体管上形成具有大应力的应力膜。该方法包括以下步骤：在其上形成有n-MOSFET的衬底的整个表面上沉积拉伸应力膜; 通过蚀刻沉积的应力膜同时将其留在n-MOSFET上去除; 对剩余的应力膜进行紫外线照射。通过UV照射，应力膜的拉伸应力提高。此外，虽然通过UV照射使应力膜固化，但是由于在蚀刻之后进行UV照射，因此防止了由固化引起的蚀刻缺陷的发生。因此，可以获得n-MOSFET的加速和高质量。

4. 发明申请

US20080054366A1 CMOS semiconductor device having tensile and compressive stress films 审中-公开
标题翻译： CMOS半导体器件具有拉伸和压应力膜
公开(公告)号：US20080054366A1
公开(公告)日：2008-03-06
申请号：US11790956
申请日：2007-04-30
申请人： Sergey Pidin
发明人： Sergey Pidin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823807 , H01L29/7843
摘要： A CMOS semiconductor device includes: an isolation region formed in the surface layer of a semiconductor substrate to define an NMOSFET active region and a PMOSFET active region adjacent to each other; an NMOSFET structure formed in the NMOSFET active region; a PMOSFET structure formed in the PMOSFET active region; a tensile stress film covering the NMOSFET structure; and a compressive stress film covering the PMOSFET structure, wherein a border between the tensile stress film and the compressive stress film is set nearer to the PMOSFET active region than the NMOSFET active region along a gate width direction. A performance of a CMOS semiconductor device can be improved by the layout of the tensile and compressive stress films.
摘要翻译： CMOS半导体器件包括：形成在半导体衬底的表面层中以限定相邻的NMOSFET有源区和PMOSFET有源区的隔离区; 形成在NMOSFET有源区中的NMOSFET结构; 形成在PMOSFET有源区中的PMOSFET结构; 覆盖NMOSFET结构的拉伸应力膜; 以及覆盖PMOSFET结构的压缩应力膜，其中拉伸应力膜和压应力膜之间的边界设置为比栅极宽度方向上的NMOSFET有源区更靠近PMOSFET有源区。可以通过拉伸和压缩应力膜的布局来改善CMOS半导体器件的性能。

5. 发明授权

US08395222B2 MOS transistor, manufacturing method thereof, and semiconductor device 有权
标题翻译： MOS晶体管及其制造方法和半导体器件
公开(公告)号：US08395222B2
公开(公告)日：2013-03-12
申请号：US13075691
申请日：2011-03-30
申请人： Sergey Pidin
发明人： Sergey Pidin
IPC分类号： H01L21/70
CPC分类号： H01L29/4991 , H01L21/823807 , H01L21/823864 , H01L27/092 , H01L29/4983 , H01L29/66515 , H01L29/6653 , H01L29/66553 , H01L29/6659 , H01L29/7843
摘要： A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode. The accumulated stress is the tensile stress if the conductivity type is an n-type, and is a compressive stress if the conductivity type is a p-type.
摘要翻译： MOS晶体管具有在由栅电极限定的沟道区域的第一侧上的硅衬底上形成的第一应力层，以及在沟道区的第二侧上形成在硅衬底上的第二应力层，第一和第二应力层根据MOS晶体管的导电类型累积拉伸应力或压缩应力。第一应力层具有第一延伸部分，该第一延伸部分沿着栅电极的第一侧壁从沟道区域附近的硅衬底向上升起，但与栅电极的第一侧壁分离，并且第二应力层具有向上升的第二延伸部分从栅极电极的第二侧壁处的沟道区域附近的硅衬底开始，但是与栅电极的第二侧壁分离。如果导电类型为n型，累积应力为拉伸应力，如果导电类型为p型，则为应力。

6. 发明授权

US07492014B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07492014B2
公开(公告)日：2009-02-17
申请号：US11150121
申请日：2005-06-13
申请人： Sergey Pidin
发明人： Sergey Pidin
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/76802 , H01L21/76832 , H01L21/76834 , H01L21/823828 , H01L21/823864 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device wherein the same metal gate material is used for both an n-channel CMOS transistor and a p-channel CMOS transistor and a manufacturing method therefor are disclosed. The n-channel transistor includes an impurity region, a first gate laminated body that has a gate oxide film and a gate electrode but does not have a gate electrode sidewall insulating film, and a first silicon nitride film that has a tensile stress and covers the surface of a semiconductor substrate and the first gate laminated body. The p-channel transistor includes an impurity region; a second gate laminated body that has a gate oxide film, a gate electrode, and a gate electrode sidewall insulating film; and a second silicon nitride film that has a compressive stress and covers the surface of the semiconductor substrate and the second gate laminated body.
摘要翻译：公开了一种半导体器件，其中相同的金属栅极材料用于n沟道CMOS晶体管和p沟道CMOS晶体管及其制造方法。 n沟道晶体管包括杂质区域，具有栅极氧化膜和栅电极但不具有栅极侧壁绝缘膜的第一栅极层叠体和具有拉伸应力的第一氮化硅膜覆盖半导体基板的表面和第一栅极层叠体。 p沟道晶体管包括杂质区; 具有栅极氧化膜，栅极电极和栅电极侧壁绝缘膜的第二栅极层叠体; 以及具有压缩应力并覆盖半导体基板和第二栅极层叠体的表面的第二氮化硅膜。

7. 发明授权

US07262472B2 Semiconductor device having stress and its manufacture method 有权
标题翻译：具有应力的半导体器件及其制造方法
公开(公告)号：US07262472B2
公开(公告)日：2007-08-28
申请号：US10970158
申请日：2004-10-22
申请人： Sergey Pidin
发明人： Sergey Pidin
IPC分类号： H01L29/76
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A semiconductor device has: active regions including a p-type active region; an insulated gate electrode structure formed on each of the active regions, and having a gate insulating film and a gate electrode formed thereon; side wall spacers formed on side walls of the insulated gate electrode structures; source/drain regions having extension regions having the opposite conductivity type to that of the active region and formed on both sides of the insulated gate electrode structures and source/drain diffusion layers having the opposite conductivity type and formed in the active regions outside of the side wall spacers; first recess regions formed by digging down the n-type source/drain regions in the p-type active region from surfaces of the n-type source/drain regions; and a first nitride film having tensile stress formed covering the p-type active region and burying the first recess regions.
摘要翻译：半导体器件具有：包括p型有源区的有源区; 形成在每个有源区上的绝缘栅电极结构，其上形成栅极绝缘膜和栅电极; 形成在绝缘栅电极结构的侧壁上的侧壁间隔物; 源极/漏极区域具有与有源区域相反的导电类型的延伸区域，并且形成在绝缘栅极电极结构的两侧和具有相反导电类型的源极/漏极扩散层并形成在侧面的有源区域中墙壁垫片通过从n型源极/漏极区的表面挖掘p型有源区中的n型源极/漏极区而形成的第一凹部区域; 以及第一氮化物膜，其具有覆盖所述p型有源区并且埋入所述第一凹部区域的拉伸应力。

8. 发明申请

US20060214241A1 Semiconductor device and manufacturing method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060214241A1
公开(公告)日：2006-09-28
申请号：US11150121
申请日：2005-06-13
申请人： Sergey Pidin
发明人： Sergey Pidin
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/76802 , H01L21/76832 , H01L21/76834 , H01L21/823828 , H01L21/823864 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device wherein the same metal gate material is used for both an n-channel CMOS transistor and a p-channel CMOS transistor and a manufacturing method therefor are disclosed. The n-channel transistor includes an impurity region, a first gate laminated body that has a gate oxide film and a gate electrode but does not have a gate electrode sidewall insulating film, and a first silicon nitride film that has a tensile stress and covers the surface of a semiconductor substrate and the first gate laminated body. The p-channel transistor includes an impurity region; a second gate laminated body that has a gate oxide film, a gate electrode, and a gate electrode sidewall insulating film; and a second silicon nitride film that has a compressive stress and covers the surface of the semiconductor substrate and the second gate laminated body.
摘要翻译：公开了一种半导体器件，其中相同的金属栅极材料用于n沟道CMOS晶体管和p沟道CMOS晶体管及其制造方法。 n沟道晶体管包括杂质区域，具有栅极氧化膜和栅电极但不具有栅极侧壁绝缘膜的第一栅极层叠体和具有拉伸应力的第一氮化硅膜覆盖半导体基板的表面和第一栅极层叠体。 p沟道晶体管包括杂质区; 具有栅极氧化膜，栅极电极和栅电极侧壁绝缘膜的第二栅极层叠体; 以及具有压缩应力并覆盖半导体基板和第二栅极层叠体的表面的第二氮化硅膜。

9. 发明申请

US20110316087A1 MOS TRANSISTOR, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE 有权
标题翻译： MOS晶体管，其制造方法和半导体器件
公开(公告)号：US20110316087A1
公开(公告)日：2011-12-29
申请号：US13075691
申请日：2011-03-30
申请人： Sergey Pidin
发明人： Sergey Pidin
IPC分类号： H01L27/092 , H01L21/336 , H01L29/772
CPC分类号： H01L29/4991 , H01L21/823807 , H01L21/823864 , H01L27/092 , H01L29/4983 , H01L29/66515 , H01L29/6653 , H01L29/66553 , H01L29/6659 , H01L29/7843
摘要： A MOS transistor has a first stress layer formed over a silicon substrate on a first side of a channel region defined by a gate electrode, and a second stress layer formed over the silicon substrate on a second side of the channel region, the first and second stress layers accumulating a tensile stress or a compressive stress depending on a conductivity type of the MOS transistor. The first stress layer has a first extending part rising upward from the silicon substrate near the channel region along a first sidewall of the gate electrode but separated from the first sidewall of the gate electrode, and the second stress layer has a second extending part rising upward from the silicon substrate near the channel region along a second sidewall of the gate electrode but separated from the second sidewall of the gate electrode. The accumulated stress is the tensile stress if the conductivity type is an n-type, and is a compressive stress if the conductivity type is a p-type.
摘要翻译： MOS晶体管具有在由栅电极限定的沟道区域的第一侧上的硅衬底上形成的第一应力层，以及在沟道区的第二侧上形成在硅衬底上的第二应力层，第一和第二应力层根据MOS晶体管的导电类型累积拉伸应力或压缩应力。第一应力层具有第一延伸部分，该第一延伸部分沿着栅电极的第一侧壁从沟道区域附近的硅衬底向上升起，但与栅电极的第一侧壁分离，并且第二应力层具有向上升的第二延伸部分从栅极电极的第二侧壁处的沟道区域附近的硅衬底开始，但是与栅电极的第二侧壁分离。如果导电类型为n型，累积应力为拉伸应力，如果导电类型为p型，则为应力。

10. 发明申请

US20050269650A1 Semiconductor device having stress and its manufacture method 有权
标题翻译：具有应力的半导体器件及其制造方法
公开(公告)号：US20050269650A1
公开(公告)日：2005-12-08
申请号：US10970158
申请日：2004-10-22
申请人： Sergey Pidin
发明人： Sergey Pidin
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/76 , H01L29/78
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66636 , H01L29/7843
摘要： A semiconductor device has: active regions including a p-type active region; an insulated gate electrode structure formed on each of the active regions, and having a gate insulating film and a gate electrode formed thereon; side wall spacers formed on side walls of the insulated gate electrode structures; source/drain regions having extension regions having the opposite conductivity type to that of the active region and formed on both sides of the insulated gate electrode structures and source/drain diffusion layers having the opposite conductivity type and formed in the active regions outside of the side wall spacers; first recess regions formed by digging down the n-type source/drain regions in the p-type active region from surfaces of the n-type source/drain regions; and a first nitride film having tensile stress formed covering the p-type active region and burying the first recess regions.
摘要翻译：半导体器件具有：包括p型有源区的有源区; 形成在每个有源区上的绝缘栅电极结构，其上形成栅极绝缘膜和栅电极; 形成在绝缘栅电极结构的侧壁上的侧壁间隔物; 源极/漏极区域具有与有源区域相反的导电类型的延伸区域，并且形成在绝缘栅极电极结构的两侧和具有相反导电类型的源极/漏极扩散层并形成在侧面的有源区域中墙壁垫片通过从n型源极/漏极区的表面挖掘p型有源区中的n型源极/漏极区而形成的第一凹部区域; 以及第一氮化物膜，其具有覆盖所述p型有源区并且埋入所述第一凹部区域的拉伸应力。

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