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1. 发明授权

US07660085B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07660085B2
公开(公告)日：2010-02-09
申请号：US11358226
申请日：2006-02-22
申请人： Hiroshi Furuta , Kenji Hibino , Hidetaka Natsume , Toshikatsu Jinbo , Kiyokazu Hashimoto
发明人： Hiroshi Furuta , Kenji Hibino , Hidetaka Natsume , Toshikatsu Jinbo , Kiyokazu Hashimoto
IPC分类号： H02H3/22
CPC分类号： G11C5/14
摘要： A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.
摘要翻译：电源保护元件的常规布局不能充分地保护内部电路免受流入从厚主布线分支的窄支线的浪涌电流的影响。根据本发明的实施例的半导体器件包括围绕端子连接的电源保护元件; 与VCC焊盘或GND焊盘连接的主要配线; 从主布线分支的分支线，向半导体器件的功能块施加电源电位或地电位; 分支部分，其分支线从主布线分支; 以及与分支线连接的内部电源保护元件。

2. 发明申请

US20060187733A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060187733A1
公开(公告)日：2006-08-24
申请号：US11358226
申请日：2006-02-22
申请人： Hiroshi Furuta , Kenji Hibino , Hidetaka Natsume , Toshikatsu Jinbo , Kiyokazu Hashimoto
发明人： Hiroshi Furuta , Kenji Hibino , Hidetaka Natsume , Toshikatsu Jinbo , Kiyokazu Hashimoto
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A conventional layout of power supply protective element cannot sufficiently protect an internal circuit against a surge current that flows into a narrow branch line that branches off from a thick main wiring line. A semiconductor device according to an embodiment of the present invention includes a power supply protective element connected around a terminal; a main wiring line connected with a VCC pad or a GND pad; a branch line that branches off from the main wiring line and applies a power supply potential or a ground potential to a functional block of the semiconductor device; a branching portion at which the branch line branches off from the main wiring line; and an internal power supply protective element connected with the branch line.
摘要翻译：电源保护元件的常规布局不能充分地保护内部电路免受流入从厚主布线分支的窄支线的浪涌电流。根据本发明的实施例的半导体器件包括围绕端子连接的电源保护元件; 与VCC焊盘或GND焊盘连接的主要配线; 从主布线分支的分支线，向半导体器件的功能块施加电源电位或地电位; 分支部分，其分支线从主布线分支; 以及与分支线连接的内部电源保护元件。

3. 发明授权

US06900513B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06900513B2
公开(公告)日：2005-05-31
申请号：US10046792
申请日：2002-01-15
申请人： Hidetaka Natsume
发明人： Hidetaka Natsume
IPC分类号： H01L21/8244 , H01L27/11 , H01L31/062 , H01L27/108 , H01L29/74
CPC分类号： H01L27/11 , H01L27/1104
摘要： The present invention relates to a semiconductor memory device having a SRAM in which a memory cell comprises a pair of transmission transistors and a flip-flop circuit containing a pair of driver transistors and a pair of load transistors, wherein: a first conductive film interconnection formed from a first conductive film which is set on a semiconductor substrate, constitutes respective gate electrodes of said driver transistors, load transistors and transmission transistors; an inlaid interconnection set in a first insulating film lying on said semiconductor substrate, constitutes one of a pair of local interconnections cross-coupling a pair of input/output terminals in said flip-flop circuit; and a second conductive film interconnection formed from a second conductive film which is set on a second insulating film lying on said first insulating film, constitutes the other one of said pair of local interconnections.
摘要翻译：本发明涉及一种具有SRAM的半导体存储器件，其中存储器单元包括一对传输晶体管和包含一对驱动晶体管和一对负载晶体管的触发电路，其中：形成第一导电膜互连从设置在半导体衬底上的第一导电膜构成所述驱动晶体管，负载晶体管和透射晶体管的各个栅电极; 位于所述半导体衬底上的第一绝缘膜中的嵌入式互连构成在所述触发器电路中交叉耦合一对输入/输出端的一对局部互连之一; 并且由设置在位于所述第一绝缘膜上的第二绝缘膜上的第二导电膜形成的第二导电膜互连构成所述一对局部互连中的另一个。

4. 发明授权

US5757031A Semiconductor static memory device having a TFT load 失效
标题翻译：具有TFT负载的半导体静态存储器件
公开(公告)号：US5757031A
公开(公告)日：1998-05-26
申请号：US755777
申请日：1996-11-22
申请人： Hidetaka Natsume
发明人： Hidetaka Natsume
IPC分类号： H01L27/11 , H01L21/8244 , H01L27/10
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： Each memory cell of an SRAM has a structure in which a gate electrode of a drive MOSFET is formed by a first conductive film, a gate electrode of a load TFT is formed by a third conducive layer and a second conductive film does not exist in an area where two gate electrodes overlap with each other. After the second conductive film is subjected to patterning, a first interlayer insulating film is successively removed with the same photolithographic mask. Since the parasitic capacitance at a memory node of the memory cell is increased by thinning the insulating film between the two gate electrodes, the SRAM has an excellent resistance to soft errors.
摘要翻译： SRAM的每个存储单元具有其中驱动MOSFET的栅电极由第一导电膜形成的结构，负载TFT的栅电极由第三导电层形成，第二导电膜不存在于第两个栅电极彼此重叠的区域。在对第二导电膜进行图案化之后，用相同的光刻掩模连续地去除第一层间绝缘膜。由于通过使两个栅电极之间的绝缘膜变薄来增加存储单元的存储器节点处的寄生电容，所以SRAM具有优异的软错误抵抗性。

5. 发明申请

US20090273089A1 Method for manufacturing semiconductor device and semiconductor device 失效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20090273089A1
公开(公告)日：2009-11-05
申请号：US12458198
申请日：2009-07-02
申请人： Hiroyuki Hoshizaki , Hidetaka Natsume
发明人： Hiroyuki Hoshizaki , Hidetaka Natsume
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device in which a conductor of a bit line may be made as large in thickness as possible to reduce resistance of the bit line and to reduce capacitance across the neighboring bit lines. The device includes a first interlayer film having a first contact metal part accommodated in it, and a second interlayer film. The second interlayer film includes a trench, and is deposited on the first interlayer film. The semiconductor device also includes a metal conductor filled in and protruding above the trench, and a hard mask film deposited on the metal conductor. The semiconductor device also includes sidewalls formed on lateral surfaces of the hard mask film and the metal conductor for overlying the second interlayer film, and a third interlayer film formed above the second interlayer film inclusive of the hard mask film and the sidewalls. The device also includes a contact hole opened through the third interlayer film and the second interlayer film and in the first interlayer film to expose the first contact metal part between the sidewalls. The device further includes a second contact metal part 1 in the contact hole.
摘要翻译：可以将位线的导体制成尽可能大的厚度以降低位线的电阻并减小相邻位线之间的电容的半导体器件。该装置包括具有容纳在其中的第一接触金属部分的第一中间膜和第二中间膜。第二层间膜包括沟槽，并且沉积在第一层间膜上。半导体器件还包括填充并突出在沟槽上方的金属导体和沉积在金属导体上的硬掩模膜。半导体器件还包括形成在硬掩模膜和用于覆盖第二层间膜的金属导体的侧表面上的侧壁，以及形成在包括硬掩模膜和侧壁的第二层间膜之上的第三层间膜。该装置还包括通过第三层间膜和第二层间膜开口的接触孔，以及在第一层间膜中暴露出侧壁之间的第一接触金属部分的接触孔。该装置还包括接触孔中的第二接触金属部分1。

6. 发明授权

US07250661B2 Semiconductor memory device with plural source/drain regions 失效
标题翻译：具有多个源极/漏极区域的半导体存储器件
公开(公告)号：US07250661B2
公开(公告)日：2007-07-31
申请号：US10996456
申请日：2004-11-26
申请人： Toshifumi Takahashi , Hidetaka Natsume
发明人： Toshifumi Takahashi , Hidetaka Natsume
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L27/1104 , H01L21/84 , Y10S257/903
摘要： A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of the first conductive type. The second source/drain region of the second conductive type is formed in a second well region of the first conductive type for a pair of second MIS-type transistors of the second conductive type. The first semiconductor region of the second conductive type is formed in the first source/drain region. The second semiconductor region of the first conductive type is formed in the second source/drain region.
摘要翻译：半导体存储器件包括第一和第二源/漏区以及第一和第二半导体区。第一导电类型的第一源极/漏极区域形成在第一导电类型的一对第一MIS型晶体管的第二导电类型的第一阱区域中。第二导电类型的第二源极/漏极区域形成在第二导电类型的一对第二MIS型晶体管的第一导电类型的第二阱区域中。第二导电类型的第一半导体区域形成在第一源极/漏极区域中。第一导电类型的第二半导体区域形成在第二源极/漏极区域中。

7. 发明申请

US20050116303A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050116303A1
公开(公告)日：2005-06-02
申请号：US10996456
申请日：2004-11-26
申请人： Toshifumi Takahashi , Hidetaka Natsume
发明人： Toshifumi Takahashi , Hidetaka Natsume
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/11 , H01L29/76
CPC分类号： H01L27/1104 , H01L21/84 , Y10S257/903
摘要： A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-type transistors of the first conductive type. The second source/drain region of the second conductive type is formed in a second well region of the first conductive type for a pair of second MIS-type transistors of the second conductive type. The first semiconductor region of the second conductive type is formed in the first source/drain region. The second semiconductor region of the first conductive type is formed in the second source/drain region.
摘要翻译：半导体存储器件包括第一和第二源/漏区以及第一和第二半导体区。第一导电类型的第一源极/漏极区域形成在第一导电类型的一对第一MIS型晶体管的第二导电类型的第一阱区域中。第二导电类型的第二源极/漏极区域形成在第二导电类型的一对第二MIS型晶体管的第一导电类型的第二阱区域中。第二导电类型的第一半导体区域形成在第一源极/漏极区域中。第一导电类型的第二半导体区域形成在第二源极/漏极区域中。

8. 发明授权

US06765272B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06765272B2
公开(公告)日：2004-07-20
申请号：US10131206
申请日：2002-04-25
申请人： Hidetaka Natsume
发明人： Hidetaka Natsume
IPC分类号： H01L2976
CPC分类号： H01L21/823814 , H01L27/092 , Y10S257/903 , Y10S257/904
摘要： A semiconductor device has a gate electrode which is formed on a first conductive-type well set in semiconductor substrate, with a gate insulating film lying therebetween; a LDD structure in which, on either side of said gate electrode, there are formed a LDD region and a source/drain region; an interlayer insulating film to cover said gate electrode as well as said LDD regions; and contact sections. A contact section connecting to one side of the source/drain regions having a potential equal to a potential of said first conductive-type well is disposed so as to come into contact with the LDD region lying thereunder; and a contact section connecting to the other side of the source/drain region having a potential different from the potential of said first conductive-type well is disposed so as not to come into contact with the LDD region lying thereunder. The present invention can develop technology capable to reduce the memory cell area while suppressing the generation of the leakage, and provide a semiconductor memory device of high integration with excellent element characteristics having a low standby current.
摘要翻译：半导体器件具有形成在半导体衬底中的第一导电类型阱的栅电极，栅极绝缘膜位于其间; LDD结构，其中在所述栅电极的任一侧上形成LDD区和源极/漏极区; 覆盖所述栅极电极以及所述LDD区域的层间绝缘膜; 和联系部分。连接到具有等于所述第一导电型阱的电位的电位的源/漏区的一侧的接触部分设置成与其下方的LDD区域接触; 并且连接到具有与所述第一导电型阱的电位不同的电位的源极/漏极区域的另一侧的接触部分设置成不与其下面的LDD区域接触。本发明可以开发能够在抑制泄漏的产生的同时减小存储单元面积的技术，并且提供具有低待机电流的优异元件特性的高集成度的半导体存储器件。

9. 发明授权

US08357612B2 Method for manufacturing semiconductor device and semiconductor device 失效
公开(公告)号：US08357612B2
公开(公告)日：2013-01-22
申请号：US12458198
申请日：2009-07-02
申请人： Hiroyuki Hoshizaki , Hidetaka Natsume
发明人： Hiroyuki Hoshizaki , Hidetaka Natsume
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L27/10885 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device in which a conductor of a bit line may be made as large in thickness as possible to reduce resistance of the bit line and to reduce capacitance across the neighboring bit lines. The device includes a first interlayer film having a first contact metal part accommodated in it, and a second interlayer film. The second interlayer film includes a trench, and is deposited on the first interlayer film. The semiconductor device also includes a metal conductor filled in and protruding above the trench, and a hard mask film deposited on the metal conductor. The semiconductor device also includes sidewalls formed on lateral surfaces of the hard mask film and the metal conductor for overlying the second interlayer film, and a third interlayer film formed above the second interlayer film inclusive of the hard mask film and the sidewalls. The device also includes a contact hole opened through the third interlayer film and the second interlayer film and in the first interlayer film to expose the first contact metal part between the sidewalls. The device further includes a second contact metal part 1 in the contact hole.

10. 发明授权

US08036048B2 Semiconductor integrated circuit having DRAM word line drivers 有权
标题翻译：具有DRAM字线驱动器的半导体集成电路
公开(公告)号：US08036048B2
公开(公告)日：2011-10-11
申请号：US12256653
申请日：2008-10-23
申请人： Hiroyuki Takahashi , Hidetaka Natsume
发明人： Hiroyuki Takahashi , Hidetaka Natsume
IPC分类号： G11C7/00
CPC分类号： G11C11/4085 , G11C5/14 , G11C8/08 , G11C11/409 , G11C11/4091
摘要： A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.
摘要翻译：根据本发明的一个方面的半导体集成电路可以包括多个驱动电路，用于根据第一电源提供的第一电压或从第二电源提供的第二电压驱动相应的多个字线具有控制信号，以及多个栅极晶体管，其中每个栅极连接到多条字线中的一条字线，并且存储节点和位线之间的连接状态基于提供给字的电压而改变线连接到门。在半导体集成电路中，多个栅极晶体管的栅极氧化膜比构成多个驱动电路的晶体管的栅极氧化膜薄。

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