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1. 发明申请

US20110096667A1 PACKET COMMUNICATION DEVICE, PACKET COMMUNICATION SYSTEM, PACKET COMMUNICATION MODULE, DATA PROCESSOR, AND DATA TRANSFER SYSTEM 有权
标题翻译：分组通信设备，分组通信系统，分组通信模块，数据处理器和数据传输系统
公开(公告)号：US20110096667A1
公开(公告)日：2011-04-28
申请号：US12873893
申请日：2010-09-01
申请人： Hiroshi Arita , Yasuhiro Nakatsuka , Yasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
发明人： Hiroshi Arita , Yasuhiro Nakatsuka , Yasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
IPC分类号： H04L12/28 , H04L12/26
CPC分类号： H04L47/6255 , H04L12/44 , H04L47/10 , H04L47/2458 , H04L47/30 , H04L47/522 , H04L49/205 , H04L49/3018 , H04L49/351
摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.
摘要翻译：由CPU1生成的发送包被保存在缓冲器100a（100b）中。从从以太网820a（820b）接收的分组中，其目的地是通信设备800的分组被保存在缓冲器100a（100b）中。应该发送的分组通过MAC单元300a或300b从传送判断电路200发送到以太网820a或820b。如果传输判断电路200将来自以太网820a的分组判断为分组，则其目的地是另一个通信设备，参考目的地MAC地址，该分组通过MAC 300b被传送到以太网820b。如果传送FIFO缓冲器130a（130b）的使用率在发送FIFO缓冲器120a（130b）中保持的分组的优先级的基础上超过阈值，则传送分组的优先级顺序高于传输分组的传输分组优先于传送分组传送到以太网820a或820b。这防止了传送缓冲器装置溢出。

2. 发明授权

US07814223B2 Packet communication device, packet communication system, packet communication system, packet communication module, data processor, and data transfer system 有权
标题翻译：分组通信设备，分组通信系统，分组通信系统，分组通信模块，数据处理器和数据传输系统
公开(公告)号：US07814223B2
公开(公告)日：2010-10-12
申请号：US12010762
申请日：2008-01-29
申请人： Hiroshi Arita , Yasuhiro Nakatsuka , Yasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
发明人： Hiroshi Arita , Yasuhiro Nakatsuka , Yasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
IPC分类号： G06F13/00
CPC分类号： H04L47/6255 , H04L12/44 , H04L47/10 , H04L47/2458 , H04L47/30 , H04L47/522 , H04L49/205 , H04L49/3018 , H04L49/351
摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.
摘要翻译：由CPU1生成的发送包被保存在缓冲器100a（100b）中。从从以太网820a（820b）接收的分组中，其目的地是通信设备800的分组被保存在缓冲器100a（100b）中。应该发送的分组通过MAC单元300a或300b从传送判断电路200发送到以太网820a或820b。如果传输判断电路200将来自以太网820a的分组判断为分组，则其目的地是另一个通信设备，参考目的地MAC地址，该分组通过MAC 300b被传送到以太网820b。如果传送FIFO缓冲器130a（130b）的使用率在发送FIFO缓冲器120a（130b）中保持的分组的优先级的基础上超过阈值，则传送分组的优先级顺序高于传输分组的传输分组优先于传送分组传送到以太网820a或820b。这防止了传送缓冲器装置溢出。

3. 发明授权

US08423661B2 Packet communication device, packet communication system, packet communication module, data processor, and data transfer system 有权
公开(公告)号：US08423661B2
公开(公告)日：2013-04-16
申请号：US12873893
申请日：2010-09-01
申请人： Hiroshi Arita , Yasuhiro Nakatsuka , Yasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
发明人： Hiroshi Arita , Yasuhiro Nakatsuka , Yasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
IPC分类号： G06F13/00
CPC分类号： H04L47/6255 , H04L12/44 , H04L47/10 , H04L47/2458 , H04L47/30 , H04L47/522 , H04L49/205 , H04L49/3018 , H04L49/351
摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.

4. 发明申请

US20090092147A1 Packet communication device, packet communication system, packet communication system, packet communication module, data processor, and data transfer system 有权
标题翻译：分组通信设备，分组通信系统，分组通信系统，分组通信模块，数据处理器和数据传输系统
公开(公告)号：US20090092147A1
公开(公告)日：2009-04-09
申请号：US12010762
申请日：2008-01-29
申请人： Hiroshi Arita , Yasuhiro Nakatsuka , Tasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
发明人： Hiroshi Arita , Yasuhiro Nakatsuka , Tasuwo Watanabe , Kei Ouchi , Yoshihiro Tanaka , Toshinobu Kanai , Masanobu Tanaka , Kenji Furuhashi , Tomoaki Aoki
IPC分类号： H04L12/28
CPC分类号： H04L47/6255 , H04L12/44 , H04L47/10 , H04L47/2458 , H04L47/30 , H04L47/522 , H04L49/205 , H04L49/3018 , H04L49/351
摘要： A transmit packet generated by a CPU 1 is held in a buffer 100a (100b). From among packets received from Ethernet 820a (820b), a packet, a destination of which is a communication device 800, is held in the buffer 100a (100b). A packet which should be transmitted is transmitted from a transfer judging circuit 200 to Ethernet 820a or 820b through a MAC unit 300a or 300b. If a transfer judging circuit 200 judges a packet from the Ethernet 820a to be a packet, a destination of which is another communication device, with reference to a destination MAC address, this packet is transferred to the Ethernet 820b through MAC 300b. If a usage rate of a transferring FIFO buffer 130a (130b) exceeds a threshold value in the process of transmitting a packet held in a transmitting FIFO buffer 120a (130b) on a priority basis, the priority order of a transfer packet is made higher than that of a transmit packet so that the transfer packet is transferred to the Ethernet 820a or 820b in preference to the transmit packet. This prevents a transfer buffer means from overflowing.
摘要翻译：由CPU1生成的发送包被保存在缓冲器100a（100b）中。从从以太网820a（820b）接收的分组中，其目的地是通信设备800的分组被保存在缓冲器100a（100b）中。应该发送的分组通过MAC单元300a或300b从传送判断电路200发送到以太网820a或820b。如果传输判断电路200将来自以太网820a的分组判断为分组，则其目的地是另一个通信设备，参考目的地MAC地址，该分组通过MAC 300b被传送到以太网820b。如果传送FIFO缓冲器130a（130b）的使用率在发送FIFO缓冲器120a（130b）中保持的分组的优先级的基础上超过阈值，则传送分组的优先级顺序高于传输分组的传输分组优先于传送分组传送到以太网820a或820b。这防止了传送缓冲器装置溢出。

5. 发明申请

US20130168148A1 MULTILAYER PRINTED WIRING BOARD AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：多层印刷接线板及其制造方法
公开(公告)号：US20130168148A1
公开(公告)日：2013-07-04
申请号：US13822446
申请日：2011-11-24
申请人： Toshinobu Kanai , Ryuichi Saito , Hideki Higashitani
发明人： Toshinobu Kanai , Ryuichi Saito , Hideki Higashitani
IPC分类号： H05K1/02
CPC分类号： H05K1/0298 , H05K1/0269 , H05K3/4069 , H05K3/462 , H05K3/4638 , H05K2201/0191 , H05K2201/0355 , H05K2201/096 , H05K2201/09918 , H05K2203/068 , Y10T156/10
摘要： A multilayer wiring board includes a double-sided wiring board, an insulating substrate stacked on the double-sided wiring board, vias provided in through-holes in the insulating substrate, an outermost wiring on an upper surface of the insulating substrate, a first fiducial mark provided on the double-sided wiring board, and a second fiducial mark provided on the insulating substrate. The first fiducial mark contains a wiring of the double-sided wiring board. The second fiducial mark contains at least one via out of the vias. The first and second fiducial marks are provided for positioning the double-sided wiring board and the insulating substrate to each other. This multilayer wiring board includes layers positioned precisely.
摘要翻译：多层布线基板包括双面布线板，堆叠在双面布线板上的绝缘基板，设置在绝缘基板中的通孔中的通孔，绝缘基板的上表面上的最外布线，第一基准设置在双面布线板上的标记和设置在绝缘基板上的第二基准标记。第一个基准标记包含双面接线板的布线。第二个基准标记在通孔中至少包含一个通孔。提供第一和第二基准标记用于将双面布线板和绝缘基板彼此定位。这种多层布线板包括精确定位的层。

6. 发明申请

US20130062101A1 MULTILAYER WIRING SUBSTRATE, AND MANUFACTURING METHOD FOR MULTILAYER SUBSTRATE 审中-公开
标题翻译：多层布线基板和多层基板的制造方法
公开(公告)号：US20130062101A1
公开(公告)日：2013-03-14
申请号：US13697774
申请日：2011-06-02
申请人： Toshinobu Kanai , Ryuichi Saito , Hideki Higashitani
发明人： Toshinobu Kanai , Ryuichi Saito , Hideki Higashitani
IPC分类号： H05K1/11 , H05K1/02 , H05K1/03 , H05K3/10
CPC分类号： H05K3/4069 , H05K3/0047 , H05K3/4623 , H05K2201/096 , H05K2203/0191 , Y10T29/49155
摘要： A multilayer wiring board includes inner-layer wiring boards each having wirings on both sides thereof; electrically insulating substrates each having through-holes filled with a conductive paste;and wirings formed in the outermost layers. The wiring boards and the electrically insulating substrates are stacked alternately in such a manner that the wirings of the wiring boards are embedded in the electrically insulating substrates at both ends of the conductive paste.
摘要翻译：多层布线板包括在其两侧均布线的内层布线板; 电绝缘基板，各自具有填充有导电浆料的通孔; 和在最外层形成的布线。布线板和电绝缘基板交替堆叠，使得布线板的布线嵌入导电浆料两端的电绝缘基板中。

7. 发明申请

US20070239919A1 Communication control semiconductor device and interface system 审中-公开
标题翻译：通信控制半导体器件和接口系统
公开(公告)号：US20070239919A1
公开(公告)日：2007-10-11
申请号：US11808109
申请日：2007-06-06
申请人： Toshinobu Kanai , Masao Naruse , Naoki Hattori
发明人： Toshinobu Kanai , Masao Naruse , Naoki Hattori
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F2213/0042
摘要： Host control means (23) which performs communication control as a host, and function control means (24) which performs communication control as a function, are mounted on one semiconductor chip. With its mounting, the host control means and the function control means are configured so as to be able to operate simultaneously. There are further provided an input/output terminal to and from which a data signal transmitted/received by communication control operations of these control means, switching means (29) connected to the input/output terminal and capable of switching a path through which a transmit/receive data signal passes upon communications under the control of the host control means, and a path through which the transmit/receive data signal passes upon communications under the control of the function control means, and a switching control register (27C) which controls the state of the switching means.
摘要翻译：作为主机进行通信控制的主机控制装置（23）和作为功能进行通信控制的功能控制装置（24）安装在一个半导体芯片上。通过其安装，主机控制装置和功能控制装置被配置为能够同时操作。还提供了一个输入/输出端子，通过这些控制装置的通信控制操作而发送/接收的数据信号，与该输入/输出端子连接的切换装置（29），并且能够切换传输在主机控制装置的控制下通信的接收数据信号以及在功能控制装置的控制下通信时发送/接收数据信号通过的路径，以及控制功能的切换控制寄存器（27C）切换装置的状态。

8. 发明申请

US20080296056A1 Printed circuit board, production method therefor, electronic-component carrier board using printed circuit board, and production method therefor 审中-公开
标题翻译：印刷电路板，其制造方法，使用印刷电路板的电子部件载体板及其制造方法
公开(公告)号：US20080296056A1
公开(公告)日：2008-12-04
申请号：US12079055
申请日：2008-03-24
申请人： Tohru Kinoshita , Toshinobu Kanai
发明人： Tohru Kinoshita , Toshinobu Kanai
IPC分类号： H05K3/10 , H01R12/06
CPC分类号： H05K1/183 , H01L23/13 , H01L23/49816 , H01L23/49822 , H01L25/0657 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2225/06517 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15151 , H01L2924/15153 , H01L2924/1517 , H05K1/186 , H05K3/0044 , H05K3/4652 , H05K3/4697 , H05K2201/09481 , H05K2201/09845 , H05K2201/10515 , H05K2203/0228 , Y10T29/49155 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A printed wiring board has a substrate having a first surface and a second surface on both sides of the substrate. A cavity is provided on the first surface. The cavity caves in towards the second surface. Several bumps are formed in the cavity as protruding towards the first surface. An insulation layer is filled in the cavity. The bumps are isolated from one another by the insulation layer. The top of each bump that protrudes towards the first surface and a zone in the cavity and close to the top are exposed in the cavity without being covered by the insulation layer.
摘要翻译：印刷电路板具有在基板的两侧具有第一表面和第二表面的基板。在第一表面上设置空腔。腔朝向第二表面洞穴。在空腔中形成有朝向第一表面突出的几个凸起。绝缘层填充在空腔中。凸块通过绝缘层彼此隔离。每个凸块的朝向第一表面突出的顶部以及空腔中靠近顶部的区域暴露在空腔中而不被绝缘层覆盖。

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