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1. 发明授权

US07293692B2 Solder joint structure, soldering method, and electronic-component manufacturing apparatus using the same structure and the method 失效
标题翻译：焊接结构，焊接方法和使用相同结构和方法的电子部件制造装置
公开(公告)号：US07293692B2
公开(公告)日：2007-11-13
申请号：US10865474
申请日：2004-06-10
申请人： Hiroshi Akamatsu , Yukinori Kawamura , Hiroshi Kai , Osamu Kuramoto , Shigeru Iwasaki , Kenji Asai , Minoru Hibino
发明人： Hiroshi Akamatsu , Yukinori Kawamura , Hiroshi Kai , Osamu Kuramoto , Shigeru Iwasaki , Kenji Asai , Minoru Hibino
IPC分类号： B23K31/02
CPC分类号： H05K3/3415 , B23K3/0638 , B23K2101/42 , H05K3/3463 , H05K3/3484 , H05K2201/035 , H05K2201/10992 , H05K2203/0545 , H05K2203/111 , H05K2203/1121 , H05K2203/1476 , Y02P70/613 , Y10T428/12493
摘要： A structure of solder joint structure formed of zinc-based lead-free solder having excellent characteristics is disclosed. Between a first lead-free solder layer and a soldering pad, the following layers are formed: a tin-copper alloy layer formed on the pad; a first alloy layer formed of second lead-free layer of which main ingredients are tin and silver; and a second alloy layer formed between the first alloy layer and the first lead-free solder. This structure allows forming the solder joint structure formed of zinc-based lead-free solder having high joint strength.
摘要翻译：公开了由具有优异特性的锌基无铅焊料形成的焊点结构的结构。在第一无铅焊料层和焊盘之间形成以下层：形成在焊盘上的锡 - 铜合金层; 由主要成分为锡和银的第二无铅层形成的第一合金层; 以及形成在第一合金层和第一无铅焊料之间的第二合金层。这种结构允许形成由具有高接合强度的锌基无铅焊料形成的焊点结构。

2. 发明授权

US07973298B2 Transport/storage cask for radioactive material 有权
标题翻译：用于放射性物质的运输/储存桶
公开(公告)号：US07973298B2
公开(公告)日：2011-07-05
申请号：US12185328
申请日：2008-08-04
申请人： Jun Shimojo , Hiroshi Akamatsu , Hiroaki Taniuchi , Kenichi Mantani
发明人： Jun Shimojo , Hiroshi Akamatsu , Hiroaki Taniuchi , Kenichi Mantani
IPC分类号： G21F5/00 , G21C11/00
CPC分类号： G21F5/06 , G21F1/08 , G21F1/10 , G21F1/12 , G21F5/08 , G21F5/10 , G21Y2002/201 , G21Y2002/303 , G21Y2004/101 , G21Y2004/303
摘要： A transport/storage cask for a radioactive material has an inner shell, an outer shell and a circular gamma ray shielding layer and a circular neutron shielding layer both of which are placed between the inner shell and the outer shell. The gamma ray shielding layer is formed by aligning a plurality of gamma ray shielding blocks composed of lead in a block shape in the circumferential direction. The entire gamma ray shielding block in the axial direction is covered with a copper tube having a higher elasticity limit than the gamma ray shielding block. In the above transport/storage cask, the gamma ray shielding layer composed of lead or a lead alloy is not easily deformed.
摘要翻译：用于放射性物质的运输/储存桶具有内壳，外壳和圆形伽马射线屏蔽层以及环形中子屏蔽层，两者均放置在内壳和外壳之间。伽马射线屏蔽层通过沿圆周方向对齐由块状的铅构成的多个伽马射线屏蔽块而形成。整个伽马射线屏蔽块在轴向方向上被具有比伽马射线屏蔽块更高的弹性极限的铜管覆盖。在上述输送/储存箱中，由铅或铅合金构成的伽马射线屏蔽层不容易变形。

3. 发明申请

US20100195416A1 Anti-fuse circuit and semiconductor memory device 审中-公开
标题翻译：防熔丝电路和半导体存储器件
公开(公告)号：US20100195416A1
公开(公告)日：2010-08-05
申请号：US12656486
申请日：2010-02-01
申请人： Hiroshi Akamatsu
发明人： Hiroshi Akamatsu
IPC分类号： G11C7/00 , H03K19/0175 , G11C17/16
CPC分类号： G11C11/4074 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C17/16 , G11C29/785 , G11C2229/763
摘要： An anti-fuse circuit uses first to fifth power supplies which have first to fifth power supply voltages, respectively, in the order of highest to lowest during writing. The anti-fuse circuit includes: a first level shift circuit which is connected to the second to fourth power supplies and which converts a first logic signal that changes between the third and fourth power supply voltages into a second logic signal that changes between the second and fourth power supply voltages; a second level shift circuit which is connected to the first, second, and fourth power supplies and which converts the second logic signal into a third logic signal that changes between the first and fourth power supply voltages; a transistor having a source connected to the first power supply and a gate connected to the third logic signal; and an anti-fuse element having one end connected to the drain of the transistor and the other end connected to the fifth power supply.
摘要翻译：反熔丝电路使用在写入期间以从最高到最低的顺序分别具有第一至第五电源电压的第一至第五电源。反熔丝电路包括：第一电平移位电路，其连接到第二至第四电源，并将在第三和第四电源电压之间变化的第一逻辑信号转换成在第二和第四电源电压之间变化的第二逻辑信号，第四电源电压; 第二电平移位电路，其连接到第一，第二和第四电源，并将第二逻辑信号转换成在第一和第四电源电压之间变化的第三逻辑信号; 具有连接到第一电源的源极和连接到第三逻辑信号的栅极的晶体管; 以及一个反熔丝元件，其一端连接到晶体管的漏极，另一端连接到第五电源。

4. 发明申请

US20070037854A1 Process for preparing sulfonamide-containing indole compounds 审中-公开
标题翻译：制备含磺酰胺的吲哚化合物的方法
公开(公告)号：US20070037854A1
公开(公告)日：2007-02-15
申请号：US10571285
申请日：2004-09-01
申请人： Kenji Hayashi , Taichi Abe , Naoki Ozeki , Hiroshi Akamatsu
发明人： Kenji Hayashi , Taichi Abe , Naoki Ozeki , Hiroshi Akamatsu
IPC分类号： A61K31/4439 , A61K31/404 , C07D403/02 , C07D209/18
CPC分类号： C07D209/42
摘要： A process for preparing a compound (5a) represented by the following formula: wherein R1 and R2 each independently represent hydrogen, C1-4 alkyl, etc. and A represents cyanophenyl, etc., characterized by reacting a compound (3a) represented by the following formula: wherein R1 and R2 have the same definitions as above, with a compound represented by the formula A—SO2Cl, wherein A has the same definition as above, in the presence of a base, in a mixed solvent of water and C1-6 alkyl acetate.
摘要翻译：制备由下式表示的化合物（5a）的方法：其中R 1和R 2各自独立地表示氢，C 1-4 >烷基等，A表示氰基苯基等，其特征在于使由下式表示的化合物（3a）与其中R 1和R 2相同与式A-SO 2 Cl表示的化合物，其中A在碱存在下，在水和C 1-6烷基乙酸酯。

5. 发明授权

US5887042A Cask for a radioactive material and radiation shield 失效
标题翻译：用于放射性物质和辐射屏蔽的罐
公开(公告)号：US5887042A
公开(公告)日：1999-03-23
申请号：US899650
申请日：1997-07-24
申请人： Hiroshi Akamatsu , Hiroaki Taniuchi
发明人： Hiroshi Akamatsu , Hiroaki Taniuchi
IPC分类号： G21F1/08 , G21F5/00 , G21F5/002 , G21F5/005 , G21F5/008 , G21F9/36 , G21C19/07
CPC分类号： G21F1/085 , G21F5/00 , G21Y2002/301 , G21Y2002/302 , G21Y2004/303
摘要： A cask for a radioactive material has a single gamma ray and neutron shielding layer disposed on the outside of a vessel body, and the shielding layer is formed of the compact of a mixture of lead and a metal hydride dispersed therein. This cask can exhibit an excellent shielding effect according to the balance of radiation source intensity between gamma rays and neutrons, and can be made more compact.
摘要翻译：用于放射性材料的桶具有设置在容器主体的外侧上的单个伽马射线和中子屏蔽层，并且屏蔽层由分散在其中的铅和金属氢化物的混合物的压块形成。根据伽马射线和中子之间的辐射源强度的平衡，这种桶可以表现出优异的屏蔽效果，并且可以变得更紧凑。

6. 发明授权

US5815032A Semiconductor device capable of preventing fluctuations of substrate potential 失效
标题翻译：能够防止衬底电位波动的半导体器件
公开(公告)号：US5815032A
公开(公告)日：1998-09-29
申请号：US694440
申请日：1996-08-12
申请人： Takuya Ariki , Hiroshi Akamatsu , Shigeru Mori
发明人： Takuya Ariki , Hiroshi Akamatsu , Shigeru Mori
IPC分类号： G11C11/409 , G11C5/14 , G11C11/407 , G11C11/4074 , G11C11/408 , H01L21/822 , H01L27/04 , H03K3/01
CPC分类号： G11C5/146 , G11C11/4074
摘要： A detect circuit receives a write enable signal, a column address strobe signal and an output control signal to predetect a mode in which data is input from an input/output terminal. While a substrate potential generation circuit normally operates, a substrate potential holding circuit also operates when the detect circuit detects the mode in which data is input, so that biasing capability of a substrate potential generating portion is increased before the data is actually input from the input/output terminal.
摘要翻译：检测电路接收写使能信号，列地址选通信号和输出控制信号，以预测从输入/输出端输入数据的模式。当衬底电位产生电路正常工作时，当检测电路检测到数据输入的模式时，衬底电位保持电路也工作，使得在从输入实际输入数据之前增加衬底电位产生部分的偏置能力 /输出端子。

7. 发明授权

US5539353A Circuit for compensating for potential voltage drops caused by parasitic interconnection resistance 失效
标题翻译：用于补偿由寄生互连电阻引起的潜在电压降的电路
公开(公告)号：US5539353A
公开(公告)日：1996-07-23
申请号：US286219
申请日：1994-08-05
申请人： Takeshi Kajimoto , Hiroshi Akamatsu
发明人： Takeshi Kajimoto , Hiroshi Akamatsu
IPC分类号： G11C11/409 , G05F1/577 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/4091 , G05F1/10 , G05F3/02
CPC分类号： G11C5/145 , G05F1/577 , G11C11/4091
摘要： A differential amplifier and an NMOS transistor are provided corresponding to each load circuit. A positive input and a negative input of the differential amplifier are coupled to a first ground interconnection and a second ground interconnection, respectively. When the selected load circuit operates, the potential received by this load circuit rises by interconnection resistances of the first ground interconnection. However, the potential received by the de-selected load circuit is reduced due to the operation of its corresponding differential amplifier and transistor. As a result, a rise in the potential of the de-selected circuit caused by the operation of the selected circuit will be suppressed. The differential amplifier and transistor corresponding to the selected load circuit also operate to reduce the potential of the selected circuit, thereby to suppress the rise in such potential.
摘要翻译：对应于每个负载电路提供差分放大器和NMOS晶体管。差分放大器的正输入和负输入分别耦合到第一接地互连和第二接地互连。当所选择的负载电路工作时，由该负载电路接收的电位由第一接地互连的互连电阻上升。然而，由于其对应的差分放大器和晶体管的操作，由所选择的负载电路接收的电位降低。结果，由所选择的电路的操作引起的所选择的电路的电位的上升将被抑制。对应于所选择的负载电路的差分放大器和晶体管也可以减小所选电路的电位，从而抑制这种电位的上升。

8. 发明授权

US08730742B2 Device 有权
标题翻译：设备
公开(公告)号：US08730742B2
公开(公告)日：2014-05-20
申请号：US13443810
申请日：2012-04-10
申请人： Hiroshi Akamatsu , Shoji Kaneko
发明人： Hiroshi Akamatsu , Shoji Kaneko
IPC分类号： G11C7/00 , G11C7/10 , G11C7/12 , G11C7/22 , G11C5/14
CPC分类号： G11C29/00 , G11C5/147 , G11C7/10 , G11C7/109 , G11C7/12 , G11C7/22 , G11C7/222 , G11C8/08 , G11C8/18 , G11C11/4076 , G11C11/4085 , G11C29/023 , G11C29/12015 , G11C2029/1202
摘要： Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on the external clock signal; word lines and bit lines; amplifier circuits connected to the bit lines, respectively; and a control unit. The control unit controls, in a test operation, at least one of the word lines to repeat a selected state and an unselected state in accordance with the internal clock signal during a first period, and maintains the amplifier circuits in an active state during the first period. The control unit further controls, in a normal operation, the amplifier circuits to switch between the active state and an inactive state depending on switching between the selected state and the unselected state of the at least one of the word lines.
摘要翻译：提供一种装置，包括：接收外部时钟信号的第一终端; 连接到第一终端的时钟发生电路，以基于外部时钟信号产生内部时钟信号; 字线和位线; 分别连接到位线的放大器电路; 和控制单元。控制单元在测试操作中控制至少一个字线，以在第一周期期间根据内部时钟信号重复所选择的状态和未选择状态，并且在第一时间段期间将放大器电路维持在活动状态期。控制单元在正常操作中进一步控制放大器电路根据所选择的状态和至少一个字线的未选择状态之间的切换而在有效状态和非活动状态之间切换。

9. 发明授权

US06841549B1 Condensed imidazole compounds and a therapeutic agent for diabetes mellitus 失效
标题翻译：缩合咪唑化合物和糖尿病治疗剂
公开(公告)号：US06841549B1
公开(公告)日：2005-01-11
申请号：US10018688
申请日：2000-06-30
申请人： Osamu Asano , Hitoshi Harada , Seiji Yoshikawa , Nobuhisa Watanabe , Takashi Inoue , Tatsuo Horizoe , Nobuyuki Yasuda , Kaya Ohashi , Hiroe Minami , Junsaku Nagaoka , Manabu Murakami , Seiichi Kobayashi , Isao Tanaka , Tsutomu Kawata , Naoyuki Shimomura , Hiroshi Akamatsu , Naoki Ozeki , Toshikazu Shimizu , Kenji Hayashi , Toyokazu Haga , Shigeto Negi , Toshihiko Naito
发明人： Osamu Asano , Hitoshi Harada , Seiji Yoshikawa , Nobuhisa Watanabe , Takashi Inoue , Tatsuo Horizoe , Nobuyuki Yasuda , Kaya Ohashi , Hiroe Minami , Junsaku Nagaoka , Manabu Murakami , Seiichi Kobayashi , Isao Tanaka , Tsutomu Kawata , Naoyuki Shimomura , Hiroshi Akamatsu , Naoki Ozeki , Toshikazu Shimizu , Kenji Hayashi , Toyokazu Haga , Shigeto Negi , Toshihiko Naito
IPC分类号： A61P3/10 , A61P43/00 , C07D471/04 , C07D473/00 , C07D473/34 , C07D473/40 , A16K31/33 , C07D239/70 , C07D471/00 , C07D487/00 , A16K31/52
CPC分类号： C07D471/04 , C07D473/00 , C07D473/34 , C07D473/40
摘要： The present invention provides a preventive or therapeutic agent for diabetes mellitus and diabetic complications, which is a new type based on an adenosine A2 receptor antagonist action.That is, it provides a novel condensed imidazole compound which has an adenosine A2 receptor antagonist action, is effective for preventing or treating diabetes mellitus and diabetic complications, and is represented by the formula (I); (wherein R1 represents e.g. an amino group which may be substituted with an alkyl group; R2 represents e.g. hydrogen atom, an alkyl group, a cycloalkyl group or an alkyl group, alkenyl group or alkynyl group which may be substituted with hydrox etc.; R3 represents e.g. an optionally substituted alkyl group, alkenyl group, alkynyl group, aryl group, heteroaryl group, pyridinone group, pyrimidinone group or piperadinone group; Ar represents e.g. an optionally substituted aryl or heteroaryl group; and Q and W are the same as or different from each other and each represents N or CH), a pharmacologically acceptable salt or hydrates thereof.
摘要翻译：本发明提供了一种基于腺苷A2受体拮抗剂作用的新型糖尿病和糖尿病并发症的预防或治疗剂。即提供了具有腺苷A2受体拮抗剂作用的新颖的缩合咪唑化合物，是有效预防或治疗糖尿病和糖尿病并发症，并由式（I）表示;（其中R 1表示例如可被烷基取代的氨基; R 2表示例如氢原子，可以被羟基取代的烷基，环烷基或烷基，烯基或炔基; R 3表示例如任选取代的烷基，烯基，炔基，芳基，杂芳基，吡啶酮基，嘧啶酮基或哌嗪酮基; Ar表示例如任选取代的芳基或杂芳基; Q和W彼此相同或不同，每个代表 N或CH），其药理学上可接受的盐或其水合物。

10. 发明授权

US6163177A Semiconductor integrated circuit device having output buffer 失效
标题翻译：具有输出缓冲器的半导体集成电路器件
公开(公告)号：US6163177A
公开(公告)日：2000-12-19
申请号：US219781
申请日：1998-12-23
申请人： Motoko Hara , Hiroshi Akamatsu , Yutaka Ikeda
发明人： Motoko Hara , Hiroshi Akamatsu , Yutaka Ikeda
IPC分类号： G11C11/417 , G11C11/407 , G11C11/409 , H03K19/017 , H03K19/0175 , H03B1/00 , H03K3/00
CPC分类号： H03K19/01721
摘要： An output buffer includes an NAND circuit, a first N channel MOS transistor connected between a power supply node and an output node, a second N channel MOS transistor connected between the output node and a ground node, the first to third drive circuits, and a delay circuit. The power supply voltage is first supplied to the gate of the second N channel MOS transistor by the second drive circuit. After a delay time delayed by the delay circuit has passed, boosted voltage is supplied to the gate of the second N channel MOS transistor by the third drive circuit. Accordingly, the output buffer is not influenced by the ringing and the pull-down characteristic improves.
摘要翻译：输出缓冲器包括NAND电路，连接在电源节点和输出节点之间的第一N沟道MOS晶体管，连接在输出节点和接地节点之间的第二N沟道MOS晶体管，第一至第三驱动电路和延时电路。电源电压首先通过第二驱动电路提供给第二N沟道MOS晶体管的栅极。在延迟电路延迟的延迟时间过去之后，由第三驱动电路向第二N沟道MOS晶体管的栅极提供升压电压。因此，输出缓冲器不受振铃影响，并且下拉特性提高。

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