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    • 5. 发明申请
      US20060286733A1 Method for manufacturing a semiconductor element 有权
    • Method for manufacturing a semiconductor element
    • US20060286733A1
    • 2006-12-21
    • US11453638
    • 2006-06-14
    • Masahiro Hayashi , Takahisa Akiba , Akihiro Shiraishi
    • Masahiro Hayashi , Takahisa Akiba , Akihiro Shiraishi
    • H01L21/8234
    • H01L21/823814 , H01L21/823807 , H01L21/823857
    • A method for manufacturing a semiconductor element, comprises: (1) forming a first insulating layer for electric field relaxation that is thicker than a first gate insulating layer in a first channel region of a transistor of a first conductive type that is one of P-type and N-type polarity formed on a semiconductor silicon wafer to surround an edge of a first gate electrode in order to reduce an electric field concentrated to a region surrounding the edge of the first gate electrode because of a voltage applied to the first gate electrode and a first drain region of the transistor of the first conductive type, and forming a second insulating layer for electric field relaxation that is thicker than a second gate insulating layer in a second channel region of a transistor of a second conductive type to surround the edge of the first gate electrode in order to reduce an electric field concentrated to a region surrounding an edge of a second gate electrode because of a voltage applied to the second gate electrode and a second drain region of the transistor of the second conductive type; (2) forming a first photoresist layer in an uppermost section of the wafer; (3) forming a first resist pattern by performing first photolithography to remove the photoresist layer in a region where ion implantation of an impurity of the first conductive type is to be performed for forming a first region for electric field relaxation so as to surround the drain region of the transistor of the first conductive type and the first insulating layer for electric field relaxation; (4) removing the first resist pattern after the ion implantation of the impurity of the first conductive type by employing the first resist pattern as a mask; (5) performing first heat treatment to diffuse the impurity of the first conductive type; (6) forming a second photoresist layer in an uppermost section of the wafer; (7) forming a second resist pattern by performing second photolithography to remove the second photoresist layer in a region where ion implantation of an impurity of the second conductive type is to be performed for forming a second region for electric field relaxation so as to surround the drain region of the transistor of the second conductive type and the second insulating layer for electric field relaxation; (8) removing the second resist pattern after the ion implantation of the impurity of the second conductive type by employing the second resist pattern as a mask; and (9) performing second heat treatment to form the first region for electric field relaxation and the second region for electric field relaxation. The first region for electric field relaxation is provided by the first heat treatment to diffuse the impurity of the first conductive type in (5) and the second heat treatment in (9).
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US07223648B2 Method for manufacturing a semiconductor element 有权
    • Method for manufacturing a semiconductor element
    • 半导体元件的制造方法
    • US07223648B2
    • 2007-05-29
    • US11453638
    • 2006-06-14
    • Masahiro Hayashi , Takahisa Akira , Akihiro Shiraishi
    • Masahiro Hayashi , Takahisa Akira , Akihiro Shiraishi
    • H01L21/8238
    • H01L21/823814 , H01L21/823807 , H01L21/823857
    • A method for manufacturing a semiconductor element, comprises: (1) forming a first insulating layer for electric field relaxation that is thicker than a first gate insulating layer in a first channel region of a transistor of a first conductive type that is one of P-type and N-type polarity formed on a semiconductor silicon wafer to surround an edge of a first gate electrode in order to reduce an electric field concentrated to a region surrounding the edge of the first gate electrode because of a voltage applied to the first gate electrode and a first drain region of the transistor of the first conductive type, and forming a second insulating layer for electric field relaxation that is thicker than a second gate insulating layer in a second channel region of a transistor of a second conductive type to surround the edge of the first gate electrode in order to reduce an electric field concentrated to a region surrounding an edge of a second gate electrode because of a voltage applied to the second gate electrode and a second drain region of the transistor of the second conductive type; (2) forming a first photoresist layer in an uppermost section of the wafer.
    • 一种半导体元件的制造方法，其特征在于，包括：（1）在第一导电类型的晶体管的第一沟道区中形成比第一栅极绝缘层厚的电场弛豫的第一绝缘层， 形成在半导体硅晶片上以包围第一栅电极的边缘的类型和N型极性，以便由于施加到第一栅电极的电压而减小集中到围绕第一栅电极的边缘的区域的电场 以及第一导电类型的晶体管的第一漏极区域，并且形成第二绝缘层，用于电场弛豫，该第二绝缘层比第二导电类型晶体管的第二沟道区域中的第二栅极绝缘层厚，以围绕边缘 的第一栅电极，以便将电场集中到围绕第二栅电极的边缘的区域，因为施加到第 所述第二栅极电极和所述第二导电类型的晶体管的第二漏极区域; （2）在晶片的最上部形成第一光致抗蚀剂层。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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