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1. 发明申请

US20120079286A1 DATA PROCESSING APPARATUS 有权
标题翻译：数据处理设备
公开(公告)号：US20120079286A1
公开(公告)日：2012-03-29
申请号：US13310441
申请日：2011-12-02
申请人： Hirokazu TSURUTA , Atsuo Yamaguchi , Shigenori Miyauchi
发明人： Hirokazu TSURUTA , Atsuo Yamaguchi , Shigenori Miyauchi
IPC分类号： G06F12/14
CPC分类号： G06F21/54 , G06F21/52 , G06F21/71
摘要： A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.
摘要翻译：提供了一种数据处理装置，其检测软件对数据的伪造和数据的重写。根据本发明实施例的数据处理装置包括一个安全单元，该安全单元具有用于解密包括保密数据的加密信号的加密电路。安全单元包括压缩电路，压缩访问安全单元所用的访问信号并输出压缩结果;以及比较电路，其将从压缩电路输出的压缩结果与先前计算出的压缩结果的期望值进行比较访问信号。

2. 发明授权

US08140858B2 Data processing apparatus 有权
标题翻译：数据处理装置
公开(公告)号：US08140858B2
公开(公告)日：2012-03-20
申请号：US12401427
申请日：2009-03-10
申请人： Hirokazu Tsuruta , Atsuo Yamaguchi , Shigenori Miyauchi
发明人： Hirokazu Tsuruta , Atsuo Yamaguchi , Shigenori Miyauchi
IPC分类号： G06F21/00
CPC分类号： G06F21/54 , G06F21/52 , G06F21/71
摘要： A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.
摘要翻译：提供了一种数据处理装置，其检测软件对数据的伪造和数据的重写。根据本发明实施例的数据处理装置包括一个安全单元，该安全单元具有用于解密包括保密数据的加密信号的加密电路。安全单元包括压缩电路，压缩访问安全单元所用的访问信号并输出压缩结果;以及比较电路，其将从压缩电路输出的压缩结果与先前计算出的压缩结果的期望值进行比较访问信号。

3. 发明授权

US09092619B2 Data processing apparatus 有权
标题翻译：数据处理装置
公开(公告)号：US09092619B2
公开(公告)日：2015-07-28
申请号：US13310441
申请日：2011-12-02
申请人： Hirokazu Tsuruta , Atsuo Yamaguchi , Shigenori Miyauchi
发明人： Hirokazu Tsuruta , Atsuo Yamaguchi , Shigenori Miyauchi
IPC分类号： G06F21/54 , G06F21/52 , G06F21/71
CPC分类号： G06F21/54 , G06F21/52 , G06F21/71
摘要： A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.
摘要翻译：提供了一种数据处理装置，其检测软件对数据的伪造和数据的重写。根据本发明实施例的数据处理装置包括一个安全单元，该安全单元具有用于解密包括保密数据的加密信号的加密电路。安全单元包括压缩电路，压缩访问安全单元所用的访问信号并输出压缩结果;以及比较电路，其将从压缩电路输出的压缩结果与先前计算出的压缩结果的期望值进行比较访问信号。

4. 发明申请

US20090259856A1 DATA PROCESSING APPARATUS 有权
标题翻译：数据处理设备
公开(公告)号：US20090259856A1
公开(公告)日：2009-10-15
申请号：US12401427
申请日：2009-03-10
申请人： Hirokazu Tsuruta , Atsuo Yamaguchi , Shigenori Miyauchi
发明人： Hirokazu Tsuruta , Atsuo Yamaguchi , Shigenori Miyauchi
IPC分类号： G06F11/30
CPC分类号： G06F21/54 , G06F21/52 , G06F21/71
摘要： A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.
摘要翻译：提供了一种数据处理装置，其检测软件对数据的伪造和数据的重写。根据本发明实施例的数据处理装置包括一个安全单元，该安全单元具有用于解密包括保密数据的加密信号的加密电路。安全单元包括压缩电路，压缩访问安全单元所用的访问信号并输出压缩结果;以及比较电路，其将从压缩电路输出的压缩结果与先前计算出的压缩结果的期望值进行比较访问信号。

5. 发明授权

US07471789B2 Encryption circuit achieving higher operation speed 失效
标题翻译：加密电路实现更高的运行速度
公开(公告)号：US07471789B2
公开(公告)日：2008-12-30
申请号：US10647308
申请日：2003-08-26
申请人： Shigenori Miyauchi , Atsuo Yamaguchi
发明人： Shigenori Miyauchi , Atsuo Yamaguchi
IPC分类号： H04K1/00
CPC分类号： G06F7/72 , G06F5/01 , G06F7/723
摘要： An addition and subtraction circuit performs addition and subtraction using a carry-in signal from another operation circuit, and outputs a carry-out signal generated through addition and subtraction to another operation circuit. A right-shift circuit performs right-shift using a shift-in signal from another operation circuit, and outputs a shift-out signal generated through right-shift to another operation circuit. Therefore, even if a data length of operation data is extended, a propagation path for a carry can be shortened, and an operation clock frequency of an encryption circuit can be increased.
摘要翻译：加法和减法电路使用来自另一个操作电路的进位信号进行加法和减法，并将通过加法和减法产生的进位输出信号输出到另一个运算电路。右移电路使用来自另一个操作电路的移入信号进行右移，并将通过右移产生的移出信号输出到另一个操作电路。因此，即使扩大了操作数据的数据长度，也可以缩短进位的传播路径，能够提高加密电路的工作时钟频率。

6. 发明授权

US08619991B2 Encoding/decoding circuit 有权
公开(公告)号：US08619991B2
公开(公告)日：2013-12-31
申请号：US13172217
申请日：2011-06-29
申请人： Shigenori Miyauchi , Atsuo Yamaguchi
发明人： Shigenori Miyauchi , Atsuo Yamaguchi
IPC分类号： H04L9/00
CPC分类号： H04L9/0894 , H04L2209/12 , H04L2209/16 , H04L2209/34
摘要： An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

7. 发明申请

US20120314858A1 ENCODING/DECODING CIRCUIT 有权
标题翻译：编码/解码电路
公开(公告)号：US20120314858A1
公开(公告)日：2012-12-13
申请号：US13593133
申请日：2012-08-23
申请人： Shigenori Miyauchi , Atsuo Yamaguchi
发明人： Shigenori Miyauchi , Atsuo Yamaguchi
IPC分类号： H04L9/00
CPC分类号： H04L9/0894 , H04L2209/12 , H04L2209/16 , H04L2209/34
摘要： An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.
摘要翻译：编码/解码操作部分包括编码/解码操作电路和用于迂回编码解码操作电路的避免路径，并且可以在编码/解码操作电路中的编码或解码输入数据之间进行选择，并且迂回编码/解码操作电路以输出输入数据无变化。必须从选择器向键存储部分和初始化矢量存储部分提供一条线。利用这种结构，可以实现一种编码/解码电路，其可以抑制用于将密钥数据的内容发送到密钥存储部分和初始化向量存储部分的电线数量的增加，并且不会引起并发症电路布局。

8. 发明申请

US20110255694A1 ENCODING/DECODING CIRCUIT 有权
标题翻译：编码/解码电路
公开(公告)号：US20110255694A1
公开(公告)日：2011-10-20
申请号：US13172217
申请日：2011-06-29
申请人： Shigenori Miyauchi , Atsuo Yamaguchi
发明人： Shigenori Miyauchi , Atsuo Yamaguchi
IPC分类号： H04L9/00
CPC分类号： H04L9/0894 , H04L2209/12 , H04L2209/16 , H04L2209/34
摘要： An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.
摘要翻译：编码/解码操作部分包括编码/解码操作电路和用于迂回编码解码操作电路的避免路径，并且可以在编码/解码操作电路中的编码或解码输入数据之间进行选择，并且迂回编码/解码操作电路以输出输入数据无变化。必须从选择器向键存储部分和初始化矢量存储部分提供一条线。利用这种结构，可以实现一种编码/解码电路，其可以抑制用于将密钥数据的内容发送到密钥存储部分和初始化向量存储部分的电线数量的增加，并且不会引起并发症电路布局。

9. 发明申请

US20070014396A1 Encoding/decoding circuit 审中-公开
标题翻译：编码/解码电路
公开(公告)号：US20070014396A1
公开(公告)日：2007-01-18
申请号：US11483849
申请日：2006-07-11
申请人： Shigenori Miyauchi , Atsuo Yamaguchi
发明人： Shigenori Miyauchi , Atsuo Yamaguchi
IPC分类号： H04L9/28 , G06F12/14 , H04L9/00 , H04L9/32 , H04K1/00 , G06F11/30
CPC分类号： H04L9/0894 , H04L2209/12 , H04L2209/16 , H04L2209/34
摘要： An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding/decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.
摘要翻译：编码/解码操作部分包括编码/解码操作电路和用于迂回编码/解码操作电路的避免路径，并且可以在编码/解码操作电路中的编码或解码输入数据之间进行选择，并且将编码/解码操作电路迂回到不改变输出数据。必须从选择器向键存储部分和初始化矢量存储部分提供一条线。利用这种结构，可以实现一种编码/解码电路，其可以抑制用于将密钥数据的内容发送到密钥存储部分和初始化向量存储部分的电线数量的增加，并且不会引起并发症电路布局。

10. 发明授权

US08559634B2 Encoding/decoding circuit 有权
标题翻译：编码/解码电路
公开(公告)号：US08559634B2
公开(公告)日：2013-10-15
申请号：US13593133
申请日：2012-08-23
申请人： Shigenori Miyauchi , Atsuo Yamaguchi
发明人： Shigenori Miyauchi , Atsuo Yamaguchi
IPC分类号： H04L9/00
CPC分类号： H04L9/0894 , H04L2209/12 , H04L2209/16 , H04L2209/34
摘要： An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.
摘要翻译：编码/解码操作部分包括编码/解码操作电路和用于迂回编码解码操作电路的避免路径，并且可以在编码/解码操作电路中的编码或解码输入数据之间进行选择，并且迂回编码/解码操作电路以输出输入数据无变化。必须从选择器向键存储部分和初始化矢量存储部分提供一条线。利用这种结构，可以实现一种编码/解码电路，其可以抑制用于将密钥数据的内容发送到密钥存储部分和初始化向量存储部分的电线数量的增加，并且不会引起并发症电路布局。

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