专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090081843A1 SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：包括用于将拉伸应力施加到硅基板的门电极的半导体器件及其制造方法
公开(公告)号：US20090081843A1
公开(公告)日：2009-03-26
申请号：US12323507
申请日：2008-11-26
申请人： Hirokazu SAYAMA , Kazunobu OHTA , Hidekazu ODA , Kouhei SUGIHARA
发明人： Hirokazu SAYAMA , Kazunobu OHTA , Hidekazu ODA , Kouhei SUGIHARA
IPC分类号： H01L21/336
CPC分类号： H01L29/7845 , H01L21/26506 , H01L21/32155 , H01L21/823412 , H01L21/823418 , H01L21/823443 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L27/10805 , H01L27/10844 , H01L27/10894 , H01L27/10897 , H01L27/1104 , H01L27/1116 , H01L29/4925 , H01L29/4933 , H01L29/66477 , H01L29/665 , H01L29/7842 , H01L29/7848
摘要： A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.
摘要翻译：在硅衬底（10）上设置用于形成nMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。使用栅极（14）作为掩模，注入具有相对较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此，栅电极（14）非晶化。随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。结果，增强了nMOS晶体管的载流子迁移率。

2. 发明申请

US20070128816A1 SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE FOR APPLYING TENSILE STRESS TO SILICON SUBSTRATE, AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：包括用于将拉伸应力施加到硅基板的门电极的半导体器件及其制造方法
公开(公告)号：US20070128816A1
公开(公告)日：2007-06-07
申请号：US11671216
申请日：2007-02-05
申请人： Hirokazu SAYAMA , Kazunobu Ohta , Hidekazu Oda , Kouhei Sugihara
发明人： Hirokazu SAYAMA , Kazunobu Ohta , Hidekazu Oda , Kouhei Sugihara
IPC分类号： H01L21/336
CPC分类号： H01L29/7845 , H01L21/26506 , H01L21/32155 , H01L21/823412 , H01L21/823418 , H01L21/823443 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823835 , H01L21/823842 , H01L27/10805 , H01L27/10844 , H01L27/10894 , H01L27/10897 , H01L27/1104 , H01L27/1116 , H01L29/4925 , H01L29/4933 , H01L29/66477 , H01L29/665 , H01L29/7842 , H01L29/7848
摘要： A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.
摘要翻译：在硅衬底（10）上设置用于形成nMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。使用栅电极（14）作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此，栅电极（14）非晶化。随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。结果，增强了nMOS晶体管的载流子迁移率。

3. 发明申请

US20110275185A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE 有权
标题翻译：制造具有偏心结构的半导体器件的方法
公开(公告)号：US20110275185A1
公开(公告)日：2011-11-10
申请号：US13185624
申请日：2011-07-19
申请人： Kazunobu OTA , Hirokazu SAYAMA , Hidekazu ODA
发明人： Kazunobu OTA , Hirokazu SAYAMA , Hidekazu ODA
IPC分类号： H01L21/8238
CPC分类号： H01L29/42368 , H01L21/02164 , H01L21/0217 , H01L21/265 , H01L21/28017 , H01L21/28158 , H01L21/823814 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/517 , H01L29/518
摘要： A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
摘要翻译：提供一种制造具有NMOS和PMOS晶体管的半导体器件的方法。半导体器件可以减小短沟道效应，可以减少栅极漏极电流泄漏，并且可以减少由于栅极重叠引起的寄生电容，从而抑制电路的操作速度的降低。在低压NMOS区域（LNR）中的硅衬底（1）的表面中离子注入诸如砷的N型杂质，从而形成延伸层（61）。然后，形成氧化硅膜（OX2）以覆盖硅衬底（1）的整个表面。栅电极（51-54）侧面上的氧化硅膜（OX2）用作偏移侧壁。然后，在低压PMOS区域（LPR）中，在硅衬底（1）的表面中将硼离子注入到相对低的浓度，从而形成稍后为扩展层（62）的P型杂质层（621）。

4. 发明申请

US20120153388A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120153388A1
公开(公告)日：2012-06-21
申请号：US13313620
申请日：2011-12-07
申请人： Hirokazu SAYAMA
发明人： Hirokazu SAYAMA
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L27/088
CPC分类号： H01L21/823412 , H01L21/823418 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0922
摘要： A semiconductor device in which a reliable high voltage p-channel transistor is formed without an increase in cost and the number of manufacturing steps. The transistor includes: a semiconductor substrate having a main surface and a p-type region therein; a p-type well region located over the p-type region and in the main surface, having a first p-type impurity region to obtain a drain electrode; an n-type well region adjoining the p-type well region along the main surface and having a second p-type impurity region to obtain a source electrode; a gate electrode between the first and second p-type impurity regions along the main surface; and a p-type buried channel overlying the n-type well region and extending along the main surface. The border between the n-type and p-type well regions is nearer to the first p-type impurity region than the gate electrode end near to the first p-type impurity region.
摘要翻译：一种半导体器件，其中形成可靠的高压p沟道晶体管，而不增加成本和制造步骤的数量。晶体管包括：其中具有主表面和p型区域的半导体衬底; 位于p型区域和主表面上的p型阱区，具有第一p型杂质区域以获得漏电极; 沿着主表面邻接p型阱区并具有第二p型杂质区以获得源电极的n型阱区; 沿着主表面的第一和第二p型杂质区之间的栅电极; 以及覆盖n型阱区并沿主表面延伸的p型掩埋沟道。 n型和p型阱区之间的边界比靠近第一p型杂质区的栅电极端更靠近第一p型杂质区。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式