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1. 发明授权

US5175689A Apparatus for processing tool path to obtain workpiece examination data 失效
标题翻译：用于加工刀具路径的装置，以获得工件检验数据
公开(公告)号：US5175689A
公开(公告)日：1992-12-29
申请号：US564764
申请日：1990-08-03
申请人： Hirokazu Matsushita , Yukio Hayakawa , Yoshiteru Iwata
发明人： Hirokazu Matsushita , Yukio Hayakawa , Yoshiteru Iwata
IPC分类号： B23Q15/00 , G05B19/4063 , G05B19/4097 , G05B19/42
CPC分类号： G05B19/4207
摘要： A data processing apparatus generates data denoting a predetermined point on a virtual surface shape formed denoting the basis of digitized data on a tool path for an inverted shape work piece, to thereby facilitates examination of the size of the inverted shape work piece. That is, digitized data obtained by scanning a model shape is input and edited to prepare digitized data representing a tool path for machining a work piece. The digitized data representing the tool path is converted to prepare a numerical control working program. Work piece examination data are also prepared based on denoting an arbitrary measurement point of a scanning probe, data denoting the measuring direction at the measuring point and the digitized data representing the tool path for machining the work piece.
摘要翻译：数据处理装置产生表示在倒置的工件的刀具路径上表示数字化数据的基础的虚拟表面形状上的预定点的数据，从而有助于检查倒置的工件的尺寸。也就是说，通过扫描模型形状获得的数字化数据被输入和编辑，以准备表示用于加工工件的刀具路径的数字化数据。表示刀具路径的数字化数据被转换为准备数控工作程序。工件检查数据也是基于表示扫描探头的任意测量点，表示测量点的测量方向的数据和表示用于加工工件的刀具路径的数字化数据而准备的。

2. 发明授权

US08530321B2 Variable resistance element and manufacturing method thereof 有权
标题翻译：可变电阻元件及其制造方法
公开(公告)号：US08530321B2
公开(公告)日：2013-09-10
申请号：US13515761
申请日：2010-12-14
申请人： Takeki Ninomiya , Yoshio Kawashima , Yukio Hayakawa , Takumi Mikawa
发明人： Takeki Ninomiya , Yoshio Kawashima , Yukio Hayakawa , Takumi Mikawa
IPC分类号： H01L21/20
CPC分类号： C23C26/00 , C23C28/00 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： A variable resistance element comprises, when M is a transition metal element, O is oxygen, and x and y are positive numbers satisfying y>x; a lower electrode; a first oxide layer formed on the lower electrode and comprising MOx when a content ratio of O with respect to M is x; a second oxide layer formed on the first oxide layer and comprising MOy when a content ratio of O with respect to M is y; an upper electrode formed on the second oxide layer; a protective layer formed on the upper electrode and comprising an electrically conductive material having a composition different from a composition of the upper electrode; an interlayer insulating layer formed to cover the protective layer; and an upper contact plug formed inside an upper contact hole penetrating the interlayer insulating layer.
摘要翻译：可变电阻元件包括当M是过渡金属元素时，O是氧，x和y是满足y> x的正数; 下电极当相对于M的含量比为O时，形成在下电极上并包含MOx的第一氧化物层; 当相对于M的含量比为O时，形成在第一氧化物层上并包含MOy的第二氧化物层; 形成在所述第二氧化物层上的上电极; 形成在上电极上并具有不同于上电极的组成的组成的导电材料的保护层; 形成为覆盖保护层的层间绝缘层; 以及形成在贯穿层间绝缘层的上接触孔内部的上接触插塞。

3. 发明申请

US20130178042A1 METHOD FOR MANUFACTURING VARIABLE RESISTANCE ELEMENT 有权
标题翻译：制造可变电阻元件的方法
公开(公告)号：US20130178042A1
公开(公告)日：2013-07-11
申请号：US13809473
申请日：2012-01-30
申请人： Takeki Ninomiya , Yukio Hayakawa , Takumi Mikawa , Takeshi Takagi
发明人： Takeki Ninomiya , Yukio Hayakawa , Takumi Mikawa , Takeshi Takagi
IPC分类号： H01L45/00
CPC分类号： H01L45/1641 , G11C13/0007 , H01L45/08 , H01L45/146 , H01L45/1608 , H01L45/1675
摘要： Provided is a method for manufacturing a variable resistance element, the method including: forming a first electrode material layer above a substrate; forming a first tantalum oxide material layer; forming a second tantalum oxide material layer; forming a second electrode material layer; and annealing at least the first tantalum oxide material layer after forming the first tantalum oxide material layer and before forming the second electrode material layer, wherein an oxygen content percentage of one of the first tantalum oxide material layer and the second tantalum oxide material layer is higher than an oxygen content percentage of the other.
摘要翻译：提供一种制造可变电阻元件的方法，该方法包括：在衬底上形成第一电极材料层; 形成第一钽氧化物材料层; 形成第二钽氧化物材料层; 形成第二电极材料层; 以及在形成所述第一钽氧化物材料层之后并且在形成所述第二电极材料层之前至少退火所述第一钽氧化物材料层，其中所述第一钽氧化物材料层和所述第二氧化钽材料层中的一个的氧含量百分比较高比另一个的氧含量百分比。

4. 发明申请

US20130119344A1 NONVOLATILE STORAGE ELEMENT AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失存储元件及其制造方法
公开(公告)号：US20130119344A1
公开(公告)日：2013-05-16
申请号：US13810800
申请日：2011-10-06
申请人： Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Yoshio Kawashima , Shinichi Yoneda
发明人： Takumi Mikawa , Yukio Hayakawa , Takeki Ninomiya , Yoshio Kawashima , Shinichi Yoneda
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , H01L27/101 , H01L45/08 , H01L45/146 , H01L45/1608 , H01L45/1625
摘要： A variable resistance nonvolatile storage element includes: a first electrode; a second electrode; and a variable resistance layer having a resistance value that reversibly changes based on an electrical signal applied between the electrodes, wherein the variable resistance layer has a structure formed by stacking a first transition metal oxide layer, a second transition metal oxide layer, and a third transition metal oxide layer in this order, the first transition metal oxide layer having a composition expressed as MOx (where M is a transition metal and O is oxygen), the second transition metal oxide layer having a composition expressed as MOy (where x>y), and the third transition metal oxide layer having a composition expressed as MOz (where y>z).
摘要翻译：可变电阻非易失性存储元件包括：第一电极; 第二电极; 以及可变电阻层，其具有基于施加在所述电极之间的电信号而可逆地变化的电阻值，其中所述可变电阻层具有通过堆叠第一过渡金属氧化物层，第二过渡金属氧化物层和第三过渡金属氧化物层而形成的结构过渡金属氧化物层，第一过渡金属氧化物层具有以MOx表示的组成（其中M是过渡金属，O是氧），第二过渡金属氧化物层具有以MOy表示的组成（其中x> y ）和具有表示为MOz（其中y> z）的组成的第三过渡金属氧化物层。

5. 发明授权

US08369161B2 Semiconductor device and control method therefor 有权
标题翻译：半导体装置及其控制方法
公开(公告)号：US08369161B2
公开(公告)日：2013-02-05
申请号：US13026075
申请日：2011-02-11
申请人： Yukio Hayakawa
发明人： Yukio Hayakawa
IPC分类号： G11C16/02
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7887
摘要： A semiconductor device includes an insulation layer (14) provided on a semiconductor substrate (12), a p-type semiconductor region (16) provided on the insulation layer, an isolation region (18) provided that surrounds the p-type semiconductor region to reach the insulation layer, an n-type source region (20) and an n-type drain region (22) provided on the p-type semiconductor region, a charge storage region (30) provided above the p-type semiconductor region between the n-type source region and the n-type drain region, and an voltage applying portion that applies a different voltage to the p-type semiconductor region while any of programming, erasing and reading a different data of a memory cell that has the charge storage region is being preformed.
摘要翻译：半导体器件包括设置在半导体衬底（12）上的绝缘层（14），设置在绝缘层上的p型半导体区域（16），设置在p型半导体区域周围的隔离区域（18）到达绝缘层，设置在p型半导体区域上的n型源极区域（20）和n型漏极区域（22），设置在p型半导体区域之上的p型半导体区域上方的电荷存储区域（30） n型源极区域和n型漏极区域以及对p型半导体区域施加不同电压的电压施加部，同时对具有电荷存储器的存储单元的不同数据的编程，擦除和读取进行任何编程，区域正在执行。

6. 发明授权

US08318566B2 Method to seperate storage regions in the mirror bit device 有权
标题翻译：分离镜像位设备中存储区域的方法
公开(公告)号：US08318566B2
公开(公告)日：2012-11-27
申请号：US13156122
申请日：2011-06-08
申请人： Fumihiko Inoue , Haruki Souma , Yukio Hayakawa
发明人： Fumihiko Inoue , Haruki Souma , Yukio Hayakawa
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/11565
摘要： Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.
摘要翻译：公开了用于隔离半导体器件中的相邻电荷累积层的装置和方法。在一个实施例中，半导体器件包括形成在半导体衬底中的位线，形成在半导体衬底上的电荷累积层，形成在位线上的电荷累积层上的字线和形成在半导体衬底中的沟道区在字线之下以及位线和其相邻位线之间。对于半导体器件，电荷累积层形成在字线的宽度方向上的沟道区上方，并且字线的宽度被设定为比沟道区的端部与中心部的距离更窄在字线的长度方向上的通道区域。

7. 发明申请

US20120069632A1 CURRENT CONTROL, MEMORY ELEMENT, MEMORY DEVICE, AND PRODUCTION METHOD FOR CURRENT CONTROL ELEMENT 有权
标题翻译：电流控制，存储元件，存储器件和电流控制元件的生产方法
公开(公告)号：US20120069632A1
公开(公告)日：2012-03-22
申请号：US13321018
申请日：2011-03-10
申请人： Yukio Hayakawa , Koji Arita , Takumi Mikawa , Takeki Ninomiya
发明人： Yukio Hayakawa , Koji Arita , Takumi Mikawa , Takeki Ninomiya
IPC分类号： G11C11/00 , H01L21/66 , H01L47/00
CPC分类号： H01L27/2409 , H01L45/146
摘要： Provided is a current steering element that can prevent write didturb even when an electrical pulse with different polarities is applied and that can cause a large current to flow through a variable resistance element. The current steering element includes a first electrode (32), a second electrode (31), and a current steering layer (33). The current steering layer (33) comprises SiNx (where 0
摘要翻译：提供了即使当施加具有不同极性的电脉冲并且可能导致大电流流过可变电阻元件时也能够防止写入干扰的电流导向元件。当前的转向元件包括第一电极（32），第二电极（31）和电流转向层（33）。当前的转向层（33）包括添加有氢或氟的SiNx（其中0

8. 发明授权

US07928018B2 Plasma processing method and method for manufacturing an electronic device 失效
标题翻译：等离子体处理方法及其制造方法
公开(公告)号：US07928018B2
公开(公告)日：2011-04-19
申请号：US10594895
申请日：2005-03-31
申请人： Tadahiro Ohmi , Akinobu Teramoto , Hiroshi Yamauchi , Yukio Hayakawa
发明人： Tadahiro Ohmi , Akinobu Teramoto , Hiroshi Yamauchi , Yukio Hayakawa
IPC分类号： H01L21/31 , H01L21/469 , H01L21/02 , C23C16/00
CPC分类号： H01L21/3105 , H01J2237/3387 , H01L21/28273 , H01L21/28282 , H01L21/3143 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The application of oxynitriding treatment to electronic appliances involve the problem that N2 ions are formed to thereby damage any oxynitride film. It is intended to provide a method of plasma treatment capable of realizing high-quality oxynitriding and to provide a process for producing an electronic appliance in which use is made of the method of plasma treatment. There is provided a method of plasma treatment, comprising generating plasma with a gas for plasma excitation and introducing a treating gas in the plasma to thereby treat a treatment subject, wherein the treating gas contains nitrous oxide gas, this nitrous oxide gas introduced in a plasma of
摘要翻译：氧化氮化处理对电子设备的应用涉及形成N2离子从而损坏任何氮氧化物膜的问题。旨在提供能够实现高质量氮氧化的等离子体处理方法，并提供一种使用等离子体处理方法的电子设备的制造方法。提供了一种等离子体处理方法，包括用等离子体激发的气体产生等离子体并在等离子体中引入处理气体，从而处理处理对象，其中处理气体含有一氧化二氮气体，这种一氧化二氮气体引入等离子体的<2.24eV电子温度，从而降低了任何绝缘膜损伤的离子的产生，从而实现高质量的氮氧化。此外，提供了一种使用等离子体处理方法的电子设备的制造方法。

9. 发明申请

US20080268657A1 Plasma Processing Method and Method for Manufacturing an Electronic Device 失效
标题翻译：等离子体处理方法及其制造方法
公开(公告)号：US20080268657A1
公开(公告)日：2008-10-30
申请号：US10594895
申请日：2005-03-31
申请人： Tadahiro Ohmi , Akinobu Teramoto , Hiroshi Yamauchi , Yukio Hayakawa
发明人： Tadahiro Ohmi , Akinobu Teramoto , Hiroshi Yamauchi , Yukio Hayakawa
IPC分类号： H01L21/469 , H05H1/24
CPC分类号： H01L21/3105 , H01J2237/3387 , H01L21/28273 , H01L21/28282 , H01L21/3143 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The application of oxynitriding treatment to electronic appliances involve the problem that N2 ions are formed to thereby damage any oxynitride film. It is intended to provide a method of plasma treatment capable of realizing high-quality oxynitriding and to provide a process for producing an electronic appliance in which use is made of the method of plasma treatment. There is provided a method of plasma treatment, comprising generating plasma with a gas for plasma excitation and introducing a treating gas in the plasma to thereby treat a treatment subject, wherein the treating gas contains nitrous oxide gas, this nitrous oxide gas introduced in a plasma of
摘要翻译：对电子器件应用氧氮化处理涉及形成N 2+离子从而损坏任何氮氧化物膜的问题。旨在提供能够实现高质量氮氧化的等离子体处理方法，并提供一种使用等离子体处理方法的电子设备的制造方法。提供了一种等离子体处理方法，包括用等离子体激发的气体产生等离子体并在等离子体中引入处理气体，从而处理处理对象，其中处理气体含有一氧化二氮气体，这种一氧化二氮气体引入等离子体的<2.24eV电子温度，从而降低了任何绝缘膜损伤的离子的产生，从而实现高质量的氮氧化。此外，提供了一种使用等离子体处理方法的电子设备的制造方法。

10. 发明申请

US20080083946A1 MEMORY CELL SYSTEM WITH CHARGE TRAP 有权
标题翻译：带有电荷捕获的存储单元系统
公开(公告)号：US20080083946A1
公开(公告)日：2008-04-10
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792 , H01L21/8238
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.
摘要翻译：提供了一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，以及缝隙平面天线等离子体氧化用于形成第二绝缘体层的电荷陷阱层。

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