会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Head mount type display device
    • 头戴式显示装置
    • US06690516B2
    • 2004-02-10
    • US09772745
    • 2001-01-30
    • Hirokazu AritakeJunji TomitaSeiichi Saito
    • Hirokazu AritakeJunji TomitaSeiichi Saito
    • G02B2714
    • G02B27/0172G02B5/30G02B2027/0178
    • The head mount type display device includes an optical system having a light emitting element, a display element illuminated by the light emitting element, and an image forming element 20 for producing an image. The display element is arranged between the image forming element and the first focal point of the image forming element at a position nearer to the first focal point of the image forming element. A virtual image of the display element is formed by the image forming element 20 and the light emitted by the light emitting element is focussed on a second focal point of the image forming element. It is designed such that the eye of an observer is located on the second focal point when use. In another form, the optical system includes first and second elliptical concave mirrors with respective ones of focal points arranged at a common position.
    • 头戴式显示装置包括具有发光元件的光学系统,由发光元件照亮的显示元件和用于产生图像的图像形成元件20。 在图像形成元件和图像形成元件的第一焦点之间的显示元件位于更靠近图像形成元件的第一焦点的位置处。 由图像形成元件20形成显示元件的虚像,并且由发光元件发射的光聚焦在图像形成元件的第二焦点上。 其设计使得当使用时观察者的眼睛位于第二焦点上。 在另一种形式中,光学系统包括第一和第二椭圆形凹面镜,其中各个焦点布置在公共位置。
    • 4. 发明授权
    • Modem apparatus
    • 调制解调器
    • US08063768B2
    • 2011-11-22
    • US11792057
    • 2005-04-14
    • Yoshihiro AkeboshiSeiichi SaitoMitsuhiro Shimozawa
    • Yoshihiro AkeboshiSeiichi SaitoMitsuhiro Shimozawa
    • H04Q1/30
    • H04B3/56H04B2203/5483
    • Provided is a modem apparatus of power line communication using a power line as a transmission path. The modem apparatus includes: an amplifier for amplifying communication signals and outputting a differential signal obtained from a pair of output signals having a phase difference of 180 degrees therebetween; a signal transformer for applying the amplified communication signals to the power lines; and a balance circuit connected at the primary side of the signal transformer, for enhancing circuit balancing. The balance circuit is constituted by a variable element capable of changing an element value, and there is provided a common mode detecting circuit that detects a common mode current flowing through the secondary side of the signal transformer and that changes the element value of the variable element of the balance circuit such that the detected common mode current becomes small.
    • 提供了使用电力线作为传输路径的电力线通信的调制解调器装置。 调制解调器装置包括:放大器,用于放大通信信号并输出​​从具有180度相位差的一对输出信号获得的差分信号; 用于将放大的通信信号施加到电力线的信号变换器; 以及连接在信号变压器初级侧的平衡电路,用于增强电路平衡。 平衡电路由能够改变元件值的可变元件构成,并且提供了共模检测电路,其检测流过信号变压器次级侧的共模电流,并且改变可变元件的元件值 使得检测到的共模电流变小。
    • 5. 发明授权
    • Semiconductor device and data processor
    • 半导体器件和数据处理器
    • US08018784B2
    • 2011-09-13
    • US12636528
    • 2009-12-11
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • Yoshihiko HottaSeiichi SaitoHiroyuki HamasakiHirotaka HaraItaru Nonomura
    • G11C7/00G11C8/00
    • G06F1/3253G06F1/3237Y02D10/128Y02D10/151
    • To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.Ina data processor having a bus controller that performs timing control of access from the CPU operated in synchronization with a high-speed first clock signal to a peripheral circuit operated in synchronization with a low-speed second clock signal, a timing control circuit is provided between the peripheral circuit and the bus controller, and the bus controller causes, in response to a read instruction from the peripheral circuit, the timing control circuit to output data held by the peripheral circuit to the bus controller in synchronization with the cycle of the high-speed clock signal, causes the timing control circuit to start, in response to a write instruction directed to the peripheral circuit, writing into the peripheral circuit in synchronization with the cycle of the high-speed clock signal, and terminates the writing in synchronization with the cycle of the low-speed clock signal.
    • 提高从高速电路块访问低速电路块的速度,而不会显着增加功耗。 Ina数据处理器具有总线控制器,其执行与高速第一时钟信号同步操作的CPU的访问定时控制到与低速第二时钟信号同步操作的外围电路,时序控制电路设置在 外围电路和总线控制器以及总线控制器响应于来自外围电路的读取指令,使定时控制电路与外围电路的高周期同步地将外围电路保持的数据输出到总线控制器, 响应于针对外围电路的写入指令,使定时控制电路开始与高速时钟信号的周期同步地写入外围电路,并且与该时钟信号同步地终止写入 周期的低速时钟信号。
    • 8. 发明申请
    • ANALOG INSULATION/MULTIPLEXER
    • 模拟绝缘/多路复用器
    • US20090066401A1
    • 2009-03-12
    • US12298673
    • 2007-04-10
    • Seiichi Saito
    • Seiichi Saito
    • H03K17/16
    • H03K17/693H03F3/38H03K17/691
    • An analog insulation multiplexer not causing magnetic saturation even if a small transformer is used and having a wide use temperature range. The analog insulation multiplexer includes: a first switching element for generating a drive control signal in accordance with an external signal; a drive insulation transformer for receiving the drive control signal on a primary side via a first resistor and for delivering an insulated drive control signal from a secondary side; a second switching element for chopping an analog signal input in accordance with the insulated drive control signal; and an analog signal insulation transformer for delivering an insulated chopped analog signal on a secondary side. The analog insulation multiplexer further includes a secondary side output adjusting circuit having a second resistor connected, on the primary side of the drive insulation transformer, in parallel to the first resistor and a capacitor having one end connected to a ground and another end connected in series to the second resistor.
    • 即使使用小型变压器并具有广泛的使用温度范围,模拟绝缘多路复用器也不会引起磁饱和。 模拟绝缘多路复用器包括:第一开关元件,用于根据外部信号产生驱动控制信号; 驱动绝缘变压器,用于经由第一电阻器在初级侧接收驱动控制信号,并用于从次级侧传送绝缘的驱动控制信号; 第二开关元件,用于根据绝缘驱动控制信号斩波模拟信号输入; 以及用于在次级侧传送绝缘的斩波模拟信号的模拟信号绝缘变压器。 模拟绝缘多路复用器还包括二次侧输出调节电路,其具有在驱动绝缘变压器的初级侧与第一电阻器并联的第二电阻器,以及电容器,其一端连接到地,另一端串联连接 到第二个电阻。
    • 10. 发明申请
    • DATA PROCESSOR
    • 数据处理器
    • US20080049029A1
    • 2008-02-28
    • US11777281
    • 2007-07-12
    • Shuji KurataSeiichi SaitoYoshiyuki Matsumoto
    • Shuji KurataSeiichi SaitoYoshiyuki Matsumoto
    • G06F13/14G06K9/46G06T1/00
    • G06K9/00986G06T1/20
    • The present invention is to contribute to reduction in cost of a system performing image recognition and display control on input image data. A data processor includes a central processing unit, a graphic controller, a display controller, an image recognizing module, a memory controller capable of controlling an access to an external memory, and image data input units for inputting image data from the outside and capable of performing necessary format conversion, and the components are formed on a single semiconductor substrate. The display controller performs display control on the image data read from the external memory via the memory controller. The image data input unit stores the image data input from the outside or the image data subjected to the necessary format conversion into a first area in the external memory via the memory controller. The image recognizing module or central processing unit executes an image process using the image data in the first area or image data in a second area, obtained by performing necessary data process on the image data, and stores a result of the process in a third area in the external memory.
    • 本发明有助于降低对输入图像数据执行图像识别和显示控制的系统的成本。 数据处理器包括中央处理单元,图形控制器,显示控制器,图像识别模块,能够控制对外部存储器的访问的存储器控​​制器,以及用于从外部输入图像数据的图像数据输入单元, 执行必要的格式转换,并且在单个半导体衬底上形成组件。 显示控制器经由存储器控制器对从外部存储器读取的图像数据执行显示控制。 图像数据输入单元经由存储器控制器将从外部输入的图像数据或经过必要格式转换的图像数据存储在外部存储器中的第一区域中。 图像识别模块或中央处理单元使用第一区域中的图像数据或通过对图像数据执行必要的数据处理获得的第二区域中的图像数据来执行图像处理,并将处理结果存储在第三区域 在外部存储器中。