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1. 发明授权

US06224674B1 Seal coating mask for semiconductor element and method of use thereof 有权
标题翻译：用于半导体元件的密封涂层掩模及其使用方法
公开(公告)号：US06224674B1
公开(公告)日：2001-05-01
申请号：US09317616
申请日：1999-05-25
申请人： Hirohisa Hino , Taro Fukui , Kenji Kitamura
发明人： Hirohisa Hino , Taro Fukui , Kenji Kitamura
IPC分类号： B05C1706
CPC分类号： H01L21/56 , H01L2224/16 , H01L2224/48091 , H01L2924/01039 , H01L2924/00014
摘要： Seal coating mask for semiconductor element and method of use thereof with a seal coating mask with an opening located at a position where a semiconductor element is mounted on a wiring board. The coating mask has an annular protrusion formed along the whole periphery of the opening. A clearance of about 0.01 to 0.5 mm is formed between at least a part of the whole periphery of the annular protrusion and the front surface of the wiring board. The coating mask also includes a space portion formed on the back of the seal coating mask for cutting off cooling material outside of the annular protrusion. The coating mask is used to forcibly coat a material for sealing the semiconductor element in the front surface of the wiring board.
摘要翻译：用于半导体元件的密封涂层掩模及其使用方法，其中密封涂层掩模具有位于布线板上的半导体元件安装位置的开口。涂层掩模具有沿着开口的整个周边形成的环形突起。在环形突起的整个周边的至少一部分和布线基板的前表面之间形成约0.01至0.5mm的间隙。涂覆掩模还包括形成在密封涂层掩模的背面上的空间部分，用于切除环形突起外部的冷却材料。涂布掩模用于强制地涂覆用于密封布线板的前表面中的半导体元件的材料。

2. 发明授权

US06469074B1 Composition of cyanate ester, epoxy resin and acid anhydride 有权
标题翻译：氰酸酯，环氧树脂和酸酐的组成
公开(公告)号：US06469074B1
公开(公告)日：2002-10-22
申请号：US09577612
申请日：2000-05-25
申请人： Hirohisa Hino , Taro Fukui , Kenji Kitamura , Shinji Hashimoto , Naoki Kanagawa
发明人： Hirohisa Hino , Taro Fukui , Kenji Kitamura , Shinji Hashimoto , Naoki Kanagawa
IPC分类号： C08K336
CPC分类号： C08G73/065 , C08G59/4014 , C08G59/4284 , Y10T428/31511
摘要： Disclosed is a liquid epoxy resin composition for sealing a semiconductor device which comprises (A) a cyanic acid ester, (B) an epoxy resin, (C) an inorganic filler, (D) a metal chelate and/or a metal salt, and at least one of (E1) an acid anhydride, (E2) a dihydrazide compound and (F) a silicone resin gel, wherein at least one of components A and B is liquid at room temperature, component E1 is liquid at room temperature, and the weight ratio of component C to the total weight of the composition, the weight ratio of component A to component B, and the weight ratio of component E1, E2 or F to the total weight of the composition except component C each ranges a specific ratio.
摘要翻译：公开了一种用于密封半导体器件的液体环氧树脂组合物，其包含（A）氰酸酯，（B）环氧树脂，（C）无机填料，（D）金属螯合物和/或金属盐，以及（E1）酸酐，（E2）二酰肼化合物和（F）有机硅树脂凝胶中的至少一种，其中组分A和B中的至少一种在室温下为液体，组分E1在室温下为液体，组分C与组合物总重量的重量比，组分A与组分B的重量比以及组分E1，E2和F与组合物除外的组合物总重量的重量比分别为特定比例。

3. 发明申请

US20100147567A1 Thermosetting Resin Composition, Method of Manufacturing the Same and Circuit Board 审中-公开
标题翻译：热固性树脂组合物及其制造方法和电路板
公开(公告)号：US20100147567A1
公开(公告)日：2010-06-17
申请号：US12226872
申请日：2007-08-28
申请人： Hirohisa Hino , Taro Fukui , Hidenori Miyakawa , Atsushi Yamaguchi , Takayuki Higuchi
发明人： Hirohisa Hino , Taro Fukui , Hidenori Miyakawa , Atsushi Yamaguchi , Takayuki Higuchi
IPC分类号： H05K1/09 , B23K35/34
CPC分类号： C08K13/02 , C08K5/09 , C22C12/00 , C22C28/00 , H05K3/3442 , H05K3/3484 , H05K2201/10636 , H05K2201/10977 , Y02P70/611 , Y10T428/31511 , C08L63/00
摘要： The object of the invention is to provide a thermosetting resin composition which, in packaging an electronic circuit containing components incapable of withstanding elevated temperatures, employs low-melting solder particles, thereby enabling batch ref lowing and enabling packaging of components with excellent strength and toughness.The invention relates to a thermosetting resin composition which includes a metal filler component, a fluxing component and a thermosetting resin binder. The metal filler component includes at least one of bismuth (Bi) and indium (In), and tin (Sn). The fluxing component, which at least one of a compound of structural formula (1) below and a compound of structural formula (2) below, is used. In the above formulas, R1 to R6 are each a hydrogen or alkyl group, and X is an organic group which has a lone electron pair or double bond π electrons and is capable of coordinating with a metal.
摘要翻译：本发明的目的是提供一种热固性树脂组合物，其在包含不能耐高温的组分的电子电路中使用低熔点焊料颗粒，从而能够批量降低并且能够包装具有优异的强度和韧性的组分。本发明涉及包含金属填料组分，助熔组分和热固性树脂粘合剂的热固性树脂组合物。金属填料组分包括铋（Bi）和铟（In）和锡（Sn）中的至少一种。使用以下结构式（1）的化合物和下述结构式（2）的化合物中的至少一种的助熔组分。在上式中，R 1〜R 6各自为氢或烷基，X为具有单电子对或双键的有机基团。电子并且能够与金属配位。

4. 发明授权

US6120716A Epoxy resin sealing material for molding semiconductor chip and method for manufacturing the same 有权
标题翻译：用于模制半导体芯片的环氧树脂密封材料及其制造方法
公开(公告)号：US6120716A
公开(公告)日：2000-09-19
申请号：US147799
申请日：1999-03-10
申请人： Takanori Kushida , Akio Kobayashi , Yosuke Obata , Hironori Ikeda , Taro Fukui , Masashi Nakamura
发明人： Takanori Kushida , Akio Kobayashi , Yosuke Obata , Hironori Ikeda , Taro Fukui , Masashi Nakamura
IPC分类号： C08L63/00 , H01L23/29 , B29B9/08
CPC分类号： C08L63/00 , H01L23/293 , H01L2924/0002
摘要： An epoxy resin encapsulating material for molding in a semiconductor chip by the use of a transfer molding device. The material has constituents of an epoxy resin, a curing agent, an inorganic filler, and a release agent. The material consists of 99 wt % or more of granules having a diameter of 0.1 to 5.0 mm and 1 wt % or less of minute particles having a diameter of less than 0.1 mm. The mass of the material exhibit an angle of slide of 20 to 40.degree., which demonstrates good flowability free from clogging a passage leading to a mold cavity in the transfer molding device, thereby assuring enhanced encapsulation quality. The material is prepared firstly by kneading the encapsulating composition having the above constituents and by solidifying the composition into a semi-cured solid body of B-stage condition. The sem-cured solid body is then pulverized into pieces having a diameter of 5.0 mm or less. The pieces are composed of granules having a diameter of 0.1 mm to 5.0 mm and minute particles having a diameter of less than 0.1 mm. Subsequently, heat is applied to melt a resin component of the encapsulating composition in the surfaces of the granules while continuously moving the granules so as to entrap the minute particles in a molten phase of the resin component. Thereafter, the molten phase is cooled to obtain epoxy resin encapsulating grains coated with a resin layer incorporating the minute particles having the diameter of less than 0.1 mm.
摘要翻译： PCT No.PCT / JP97 / 02774 Sec。 371 1999年3月10日 102（e）1999年3月10日PCT PCT 1997年8月7日PCT公布。公开号WO99 / 08321 1999年2月18日，日本专利公开了一种用于通过传递模塑装置在半导体芯片中成型的环氧树脂封装材料。该材料具有环氧树脂，固化剂，无机填料和脱模剂的成分。该材料由直径为0.1〜5.0mm，直径小于0.1mm的微粒的1wt％以下的99wt％以上的颗粒构成。材料的质量表现出20〜40°的滑动角度，这表现出良好的流动性，没有堵塞通向传送模制装置中的模腔的通道，从而确保了增强的封装质量。首先通过捏合具有上述组分的包封组合物并将组合物固化成B阶状态的半固化固体物质。然后将半固化的固体粉碎成直径为5.0mm以下的片。这些片由直径为0.1mm至5.0mm的颗粒和直径小于0.1mm的微小颗粒组成。随后，在颗粒表面连续移动颗粒以使微小颗粒在树脂组分的熔融相中截留，施加热量以熔化颗粒表面中的包封组合物的树脂组分。然后，将熔融相冷却，得到涂布有直径小于0.1mm的微小粒子的树脂层的环氧树脂封装晶粒。

5. 发明授权

US07230331B2 Chip package structure and process for fabricating the same 有权
标题翻译：芯片封装结构及其制造工艺
公开(公告)号：US07230331B2
公开(公告)日：2007-06-12
申请号：US10707683
申请日：2004-01-05
申请人： Kai-Chi Chen , Shu-Chen Huang , Hsun-Tien Li , Tzong-Ming Lee , Taro Fukui , Tomoaki Nemoto
发明人： Kai-Chi Chen , Shu-Chen Huang , Hsun-Tien Li , Tzong-Ming Lee , Taro Fukui , Tomoaki Nemoto
IPC分类号： H01L23/22 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L21/565 , H01L23/3128 , H01L24/48 , H01L24/97 , H01L25/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/48091 , H01L2224/73204 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.
摘要翻译：公开了一种芯片封装结构及其制造方法。芯片封装结构主要包括载体，芯片和封装材料层。为了制造芯片封装，提供了载体和多个芯片。每个芯片至少具有在其上具有多个凸块的活性表面。芯片和载体电连接。形成填充芯片和载体之间的接合间隙并覆盖芯片和载体的封装材料层。芯片和载体之间的封装材料层具有第一厚度，并且芯片上的封装材料层具有第二厚度。第二厚度具有在第一厚度的一半到两倍之间的值。

6. 发明授权

US07057277B2 Chip package structure 有权
标题翻译：芯片封装结构
公开(公告)号：US07057277B2
公开(公告)日：2006-06-06
申请号：US10707686
申请日：2004-01-05
申请人： Kai-Chi Chen , Shu-Chen Huang , Hsun-Tien Li , Tzong-Ming Lee , Taro Fukui , Tomoaki Nemoto
发明人： Kai-Chi Chen , Shu-Chen Huang , Hsun-Tien Li , Tzong-Ming Lee , Taro Fukui , Tomoaki Nemoto
IPC分类号： H01L23/34
CPC分类号： H01L21/561 , H01L21/565 , H01L23/3128 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06582 , H01L2225/06589 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2224/81 , H01L2924/00 , H01L2224/48237 , H01L2224/0401 , H01L2924/00012
摘要： A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.
摘要翻译：公开了一种芯片封装结构。芯片封装结构基本上包括载体，一个或多个芯片，散热器和封装材料层。使用倒装芯片接合技术将至少一个芯片接合并电连接到载体或另一个芯片。在芯片和载体或其他芯片之间建立了倒装芯片接合间隙。散热器设置在顶级芯片上。散热器的面积大于芯片。封装材料层填充倒装芯片接合间隙并覆盖载体以及散热器。封装材料层在同时成型工艺中形成并具有大于1.2W / m·K的导热系数。此外，多个间隔部件可以选择性地定位在散热器上。

7. 发明授权

US07061103B2 Chip package structure 有权
标题翻译：芯片封装结构
公开(公告)号：US07061103B2
公开(公告)日：2006-06-13
申请号：US10707684
申请日：2004-01-05
申请人： Kai-Chi Chen , Shu-Chen Huang , Hsun-Tien Li , Tzong-Ming Lee , Taro Fukui , Tomoaki Nemoto
发明人： Kai-Chi Chen , Shu-Chen Huang , Hsun-Tien Li , Tzong-Ming Lee , Taro Fukui , Tomoaki Nemoto
IPC分类号： H01L23/22 , H01L23/34
CPC分类号： H01L23/4334 , H01L21/565 , H01L24/45 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2225/06589 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/15311 , H01L2924/15787 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip-chip bonded and electrically connected to the carrier or another chip. There is a flip-chip bonding gap between the chip and the carrier or other chips. A heat sink is positioned on the uppermost chip. The encapsulating material layer fills the flip-chip bonding gap as well as a gap between the uppermost chip and the heat sink. A part of the surface of the heat sink away from the upper-most chip is exposed. Furthermore, the encapsulating material layer is formed in a simultaneous molding process. For example, the chip is separated from the heat sink by a distance between 0.03˜0.2 mm, and the encapsulating material has a thermal conductivity greater than 1.2 W/m.K.
摘要翻译：公开了一种芯片封装结构。芯片封装结构基本上包括载体，一个或多个芯片，散热器和封装材料层。芯片中的至少一个被倒装芯片结合并电连接到载体或另一个芯片。在芯片和载体或其他芯片之间存在倒装芯片接合间隙。散热器位于最上面的芯片上。封装材料层填充倒装芯片接合间隙以及最上面的芯片和散热器之间的间隙。离开最上面的芯片的散热器表面的一部分被暴露。此外，封装材料层以同时成型工艺形成。例如，将芯片与散热器隔开0.03〜0.2mm的距离，封装材料的导热率大于1.2W / m·K。

8. 发明授权

US5401812A Thermosetting polyimide composition, thermoset product thereof and manufacturing process thereof 失效
标题翻译：热固性聚酰亚胺组合物，其热固性产物及其制备方法
公开(公告)号：US5401812A
公开(公告)日：1995-03-28
申请号：US994226
申请日：1992-12-21
申请人： Hiroshi Yamamoto , Taro Fukui
发明人： Hiroshi Yamamoto , Taro Fukui
IPC分类号： C08L79/08 , C08L79/06
CPC分类号： C08L79/085 , Y10S525/928
摘要： A thermosetting polyimide composition is provided with a sufficient heat resistance and excellent mechanical and electrical characteristics in toughness, flexibility and so on and under severe environmental conditions, by adding to a polyfunctional unsaturated imide a thermosetting resin selected from the group consisting of polyetherimide, polyarylate and polyamideimide which are in a miscibility region with the polyfunctional unsaturated imide and have an excellent glass transition point and a number-average molecular weight of more than 10,000.
摘要翻译：热固性聚酰亚胺组合物通过向多官能不饱和酰亚胺中加入选自聚醚酰亚胺，多芳基化合物和聚醚酰亚胺的热固性树脂，在韧性，柔韧性等以及恶劣的环境条件下具有足够的耐热性和优异的机械和电学特性聚酰胺酰亚胺，其与多官能不饱和酰亚胺处于混溶性区域，并且具有优异的玻璃化转变点和数均分子量大于10,000。

9. 发明申请

US20070072339A1 PROCESS FOR FABRICATING CHIP PACKAGE STRUCTURE 审中-公开
标题翻译：制造芯片包装结构的过程
公开(公告)号：US20070072339A1
公开(公告)日：2007-03-29
申请号：US11309106
申请日：2006-06-23
申请人： Kai-Chi Chen , Shu-Chen Huang , Hsun-Tien Li , Tzong-Ming Lee , Taro Fukui , Tomoaki Nemoto
发明人： Kai-Chi Chen , Shu-Chen Huang , Hsun-Tien Li , Tzong-Ming Lee , Taro Fukui , Tomoaki Nemoto
IPC分类号： H01L21/00
CPC分类号： H01L23/4334 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45124 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19043 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A process for fabricating a chip package structure is disclosed. To fabricate the chip package structure, a carrier and a plurality of chips are provided. Each chip has an active surface and at least one of the active surfaces has a plurality of bumps thereon. The chips and the carrier are electrically connected together. Thereafter, a heat sink is attached to the back of the chips and then at least one heat-resistant buffering film is formed over part of the heat sink surface. An encapsulating material layer is formed over the carrier and filling bonding gaps between the chips and the carrier. The encapsulating material within the bonding gaps has a thickness. The maximum diameter of particles constituting the encapsulating material layer is less than half of the said thickness.
摘要翻译：公开了一种用于制造芯片封装结构的工艺。为了制造芯片封装结构，提供了载体和多个芯片。每个芯片具有活性表面，并且活性表面中的至少一个在其上具有多个凸块。芯片和载体电连接在一起。此后，将散热器附接到芯片的背面，然后在散热器表面的一部分上形成至少一个耐热缓冲膜。在载体上形成封装材料层，并填充芯片和载体之间的接合间隙。接合间隙内的封装材料具有厚度。构成封装材料层的颗粒的最大直径小于所述厚度的一半。

10. 发明申请

US20060261499A1 CHIP PACKAGE STRUCTURE 审中-公开
标题翻译：芯片包装结构
公开(公告)号：US20060261499A1
公开(公告)日：2006-11-23
申请号：US11462369
申请日：2006-08-04
申请人： Kai-Chi Chen , Shu-Chen Huang , Hsun-Tien Li , Tzong-Ming Lee , Taro Fukui , Tomoaki Nemoto
发明人： Kai-Chi Chen , Shu-Chen Huang , Hsun-Tien Li , Tzong-Ming Lee , Taro Fukui , Tomoaki Nemoto
IPC分类号： H01L23/28
CPC分类号： H01L25/0657 , H01L21/565 , H01L23/3128 , H01L24/48 , H01L24/97 , H01L25/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/48091 , H01L2224/73204 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.
摘要翻译：公开了一种芯片封装结构及其制造方法。芯片封装结构主要包括载体，芯片和封装材料层。为了制造芯片封装，提供了载体和多个芯片。每个芯片至少具有在其上具有多个凸块的活性表面。芯片和载体电连接。形成填充芯片和载体之间的接合间隙并覆盖芯片和载体的封装材料层。芯片和载体之间的封装材料层具有第一厚度，并且芯片上的封装材料层具有第二厚度。第二厚度具有在第一厚度的一半到两倍之间的值。

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