专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5394338A Module cell generating device for a semiconductor integrated circuit 失效
标题翻译：用于半导体集成电路的模块单元产生装置
公开(公告)号：US5394338A
公开(公告)日：1995-02-28
申请号：US805139
申请日：1991-12-11
申请人： Hirofumi Shinohara , Hiroyuki Amishiro
发明人： Hirofumi Shinohara , Hiroyuki Amishiro
IPC分类号： G06F17/50 , G06F15/60
CPC分类号： G06F17/5068
摘要： A module cell generating device of a semiconductor integrated circuit includes a parameter input part for applying a designation parameter, a basic cell group storing the basic cells, and a basic cell arranging and wiring process part for generating layout designing data by utilizing a structure description part which is a control description for defining the arrangement method and the wiring method of the basic cells, the designation parameter, the structure description, and the basic cells. Furthermore, it includes a basic cell generating process part for generating the newly designated basic cells in accordance with the designation parameter.
摘要翻译：半导体集成电路的模块单元产生装置包括用于应用指定参数的参数输入部分，存储基本单元的基本单元组，以及用于通过利用结构描述部分来生成布局设计数据的基本单元布置和布线处理部分这是用于定义基本单元的布置方法和布线方法的控制描述，指定参数，结构描述和基本单元。此外，它包括用于根据指定参数生成新指定的基本单元的基本单元产生处理部分。

2. 发明授权

US06835647B2 Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method 失效
标题翻译：包括多个互连层的半导体器件，其制造方法和制造方法中使用的半导体电路的设计方法
公开(公告)号：US06835647B2
公开(公告)日：2004-12-28
申请号：US10382902
申请日：2003-03-07
申请人： Hiroyuki Amishiro , Motoshige Igarashi
发明人： Hiroyuki Amishiro , Motoshige Igarashi
IPC分类号： H01L214763
CPC分类号： H01L23/5283 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer. A second insulator is formed to surround the second interconnection layer and has a dielectric constant higher than the first insulator.
摘要翻译：提供一种包括具有优异的电气特性并且即使当其小型化也允许更高的操作速度和更低的功率消耗的互连结构的半导体器件，并且提供了制造方法中使用的半导体电路的设计方法。在半导体器件中，在半导体衬底的主表面上形成导电区域。第一互连层电连接到导电区域，具有相对短的线路长度，并且包含具有相对较高电阻的材料。形成第一绝缘体以包围第一互连层并且具有相对低的介电常数。第二互连层形成在半导体衬底的主表面上，包含比第一互连层中包含的材料低的电阻，并且具有比第一互连层更长的线长度。形成第二绝缘体以包围第二互连层并且具有高于第一绝缘体的介电常数。

3. 发明授权

US07821078B2 Semiconductor device having resistor elements and method for manufacturing the same 有权
标题翻译：具有电阻元件的半导体器件及其制造方法
公开(公告)号：US07821078B2
公开(公告)日：2010-10-26
申请号：US12007496
申请日：2008-01-11
申请人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
摘要翻译：本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。有源区靠近电阻元件配置。这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

4. 发明授权

US06779160B2 Apparatus, method and pattern for evaluating semiconductor device characteristics 失效
标题翻译：用于评估半导体器件特性的装置，方法和图案
公开(公告)号：US06779160B2
公开(公告)日：2004-08-17
申请号：US10345950
申请日：2003-01-17
申请人： Hiroyuki Amishiro , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Kenji Yamaguchi
IPC分类号： G06F1750
CPC分类号： G01R31/2621 , G01R27/02 , G01R31/2648 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： External resistance Rsd1 is obtained using a first evaluation pattern of MOSFETs having a gate contact length Lgc1 and a channel width W1 each (in steps 100 and 102). External resistance Rsd2 is then acquired by use of a second evaluation pattern of MOSFETs having a gate contact length Lgc2 and a channel width W2 each (in steps 100 and 104). Thereafter, sheet resistance Rsh and overlapping portion resistance Rdsw of the MOSFETs are computed (in step 106) in accordance with the following expressions: Rsh=(W2·Rsd2−W1·Rsd1)/(Lgc2−Lgc1) Rdsw=(W1·Lgc2·Rsd1−W2·Lgc1·Rsd2)/(Lgc2−Lgc1).
摘要翻译：使用具有栅极接触长度Lgc1和沟道宽度W1的MOSFET的第一评估模式（步骤100和102）获得外部电阻Rsd1。然后通过使用具有栅极接触长度Lgc2和沟道宽度W2的MOSFET的第二评估模式（步骤100和104）来获取外部电阻Rsd2。此后，根据以下表达式计算MOSFET的薄层电阻Rsh和重叠部分电阻Rdsw（在步骤106中）：

5. 发明授权

US06407573B1 Device for evaluating characteristic of insulated gate transistor 失效
标题翻译：绝缘栅晶体管特性评估装置
公开(公告)号：US06407573B1
公开(公告)日：2002-06-18
申请号：US09238887
申请日：1999-01-28
申请人： Kenji Yamaguchi , Hiroyuki Amishiro , Yuko Maruyama
发明人： Kenji Yamaguchi , Hiroyuki Amishiro , Yuko Maruyama
IPC分类号： G01R3126
CPC分类号： G01R31/2621 , H01L2924/0002 , H01L2924/00
摘要： A transistor having a longer channel length and serving as a reference, and a transistor having a shorter channel length and to be subjected to effective channel length extraction are prepared (step ST1.1). A hypothetical point at which a change in a total drain-to-source resistance is estimated to be approximately zero when a gate overdrive is slightly changed is extracted in a mask channel length versus total drain-to-source resistance plane. The values of a function (F) are calculated which are defined by the difference between the rate of change in the total drain-to-source resistance and the product of a channel resistance per unit length and the rate of change in a mask channel length at the hypothetical points (step ST1.6). A true threshold voltage of the transistor having the shorter channel length is determined by a shift amount (&dgr;) which minimizes the standard deviation of the function (F) determined in the step ST1.7 (step ST1.10). A resistance-based method thus extracts an effective channel length and a series resistance with increased accuracy.
摘要翻译：制备具有较长沟道长度并用作基准的晶体管，以及具有较短沟道长度并经受有效沟道长度提取的晶体管（步骤ST1.1）。当栅极过驱动略微改变时，估计总漏极 - 源极电阻的变化大致为零的假想点，掩模沟道长度对总漏极 - 源极电阻平面提取。计算函数（F）的值，其由总漏极 - 源极电阻的变化率与每单位长度的沟道电阻的乘积与掩模沟道长度的变化率之间的差定义在假想点（步骤ST1.6）。具有较短信道长度的晶体管的真实阈值电压由步骤ST1.7中确定的函数（F）的标准偏差最小化的移位量（delta）确定（步骤ST1.10）。因此，基于电阻的方法提高了精确度的有效通道长度和串联电阻。

6. 发明授权

US6037630A Semiconductor device with gate electrode portion and method of manufacturing the same 失效
标题翻译：具有栅电极部分的半导体器件及其制造方法
公开(公告)号：US6037630A
公开(公告)日：2000-03-14
申请号：US976076
申请日：1997-11-21
申请人： Motoshige Igarashi , Hiroyuki Amishiro , Keiichi Higashitani
发明人： Motoshige Igarashi , Hiroyuki Amishiro , Keiichi Higashitani
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78 , H01L27/088
CPC分类号： H01L29/6659 , H01L21/28114 , H01L29/42376 , H01L29/4916 , H01L29/7833 , H01L29/7836 , H01L21/28035 , Y10S257/90
摘要： A first polysilicon film which contains phosphorus as an impurity is formed on a semiconductor substrate. A second polysilicon film which is higher in phosphorus concentration than the first polysilicon film is formed on the first polysilicon film. The second polysilicon film is anisotropically etched to expose a surface of the first polysilicon film. Thermal oxidation is then performed. A surface of the first polysilicon film and a surface of the second polysilicon film are oxidized according to their respective oxidization rates depending on their respective phosphorus concentrations. Thus, a semiconductor device in which the size of the gate electrode can be readily controlled and damage to the semiconductor substrate or the like can be suppressed, is obtained.
摘要翻译：在半导体衬底上形成含有磷作为杂质的第一多晶硅膜。在第一多晶硅膜上形成磷浓度高于第一多晶硅膜的第二多晶硅膜。第二多晶硅膜被各向异性蚀刻以暴露第一多晶硅膜的表面。然后进行热氧化。第一多晶硅膜的表面和第二多晶硅膜的表面根据它们各自的氧化速率而被氧化，这取决于它们各自的磷浓度。因此，可以抑制其中可以容易地控制栅电极的尺寸并损害半导体衬底等的半导体器件。

7. 发明授权

US5600170A Interconnection structure of semiconductor device 失效
标题翻译：半导体器件的互连结构
公开(公告)号：US5600170A
公开(公告)日：1997-02-04
申请号：US479735
申请日：1995-06-07
申请人： Masao Sugiyama , Hiroyuki Amishiro , Keiichi Higashitani
发明人： Masao Sugiyama , Hiroyuki Amishiro , Keiichi Higashitani
IPC分类号： H01L23/522 , H01L21/768 , H01L23/485 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L23/485 , H01L21/768 , H01L21/76895 , H01L29/41775 , H01L29/456 , H01L29/49 , H01L2924/0002
摘要： An interconnection structure of a semiconductor device with a gate electrode, an active region provided in the vicinity of the gate electrode and a first buried layer in a contact hole exposing the gate electrode and the active region. The contact hole is easily formed, and the first buried layer has a substantially low interconnection resistance value.
摘要翻译：具有栅电极的半导体器件的互连结构，设置在栅电极附近的有源区和露出栅电极和有源区的接触孔中的第一掩埋层。接触孔容易形成，并且第一掩埋层具有基本上较低的互连电阻值。

8. 发明申请

US20080116526A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080116526A1
公开(公告)日：2008-05-22
申请号：US12007496
申请日：2008-01-11
申请人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Toshio Kumamoto , Motoshige Igarashi , Kenji Yamaguchi
IPC分类号： H01L27/06
CPC分类号： H01L27/0207 , H01L27/0629 , H01L27/0802 , H01L28/20
摘要： A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.
摘要翻译：本发明的半导体器件具有在半导体衬底的表面上的预定区域中的元件隔离氧化膜上形成的多个电阻元件。有源区靠近电阻元件配置。这允许电阻元件附近的元件隔离氧化膜被分成合适的条，在通过CMP抛光膜时防止元件隔离氧化膜中心处的凹陷形成，从而提高制造时电阻器元件的尺寸精度。

9. 发明授权

US06541862B2 Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method 失效
公开(公告)号：US06541862B2
公开(公告)日：2003-04-01
申请号：US09907675
申请日：2001-07-19
申请人： Hiroyuki Amishiro , Motoshige Igarashi
发明人： Hiroyuki Amishiro , Motoshige Igarashi
IPC分类号： H01L2348
CPC分类号： H01L23/5283 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer. A second insulator is formed to surround the second interconnection layer and has a dielectric constant higher than the first insulator.

10. 发明授权

US06518592B1 Apparatus, method and pattern for evaluating semiconductor device characteristics 失效
标题翻译：用于评估半导体器件特性的装置，方法和图案
公开(公告)号：US06518592B1
公开(公告)日：2003-02-11
申请号：US09713338
申请日：2000-11-16
申请人： Hiroyuki Amishiro , Kenji Yamaguchi
发明人： Hiroyuki Amishiro , Kenji Yamaguchi
IPC分类号： H01L2358
CPC分类号： G01R31/2621 , G01R27/02 , G01R31/2648 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： External resistance Rsd1 is obtained using a first evaluation pattern of MOSFETs having a gate contact length Lgc1 and a channel width W1 each (in steps 100 and 102). External resistance Rsd2 is then acquired by use of a second evaluation pattern of MOSFETs having a gate contact length Lgc2 and a channel with W2 each (in steps 100 and 104). Thereafter, sheet resistance Rsh and overlapping portion resistance Rdsw of the MOSFETs are computed (in step 106) in accordance with the following expressions: Rsh=(W2Rsd2−W1·Rsd1)/(Lgc2−Lgc1) Rdsw=(W1Lgc2·Rsd1−W2·Lgc1·Rsd2)/(Lgc2−Lgc1)
摘要翻译：使用具有栅极接触长度Lgc1和沟道宽度W1的MOSFET的第一评估模式（步骤100和102）获得外部电阻Rsd1。然后通过使用具有栅极接触长度Lgc2的MOSFET的第二评估模式和各自的沟道（步骤100和104）来获取外部电阻Rsd2。此后，根据以下表达式计算MOSFET的薄层电阻Rsh和重叠部分电阻Rdsw（在步骤106中）：

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式