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1. 发明授权

US08400237B2 Circuit device including a nano-composite dielectric film 失效
标题翻译：包括纳米复合电介质膜的电路装置
公开(公告)号：US08400237B2
公开(公告)日：2013-03-19
申请号：US12681284
申请日：2008-07-29
申请人： Hiroaki Ueno , Hiroyuki Sakai , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Hiroaki Ueno , Hiroyuki Sakai , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01P3/08
CPC分类号： H01L21/02118 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/312 , H01L23/5222 , H01L23/5223 , H01L23/66 , H01L28/40 , H01L2223/6627 , H01L2223/6644 , H01L2924/0002 , H01L2924/19032 , H01L2924/3011 , H01P3/003 , H01P3/081 , H01L2924/00
摘要： A circuit device includes a substrate 11, and a transmission line 10. The transmission line 10 includes a dielectric film 13 formed on the substrate 11, and a signal line formed on the dielectric film 13. The dielectric film 13 includes a nano-composite film in which particles of a first material are dispersed in a second material.
摘要翻译：电路装置包括基板11和传输线10.传输线10包括形成在基板11上的电介质膜13和形成在电介质膜13上的信号线。电介质膜13包括纳米复合膜其中第一材料的颗粒分散在第二材料中。

2. 发明申请

US20100237967A1 CIRCUIT DEVICE 失效
标题翻译：电路设备
公开(公告)号：US20100237967A1
公开(公告)日：2010-09-23
申请号：US12681284
申请日：2008-07-29
申请人： Hiroaki Ueno , Hiroyuki Sakai , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Hiroaki Ueno , Hiroyuki Sakai , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01P3/08
CPC分类号： H01L21/02118 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/312 , H01L23/5222 , H01L23/5223 , H01L23/66 , H01L28/40 , H01L2223/6627 , H01L2223/6644 , H01L2924/0002 , H01L2924/19032 , H01L2924/3011 , H01P3/003 , H01P3/081 , H01L2924/00
摘要： A circuit device includes a substrate 11, and a transmission line 10. The transmission line 10 includes a dielectric film 13 formed on the substrate 11, and a signal line formed on the dielectric film 13. The dielectric film 13 includes a nano-composite film in which particles of a first material are dispersed in a second material.
摘要翻译：电路装置包括基板11和传输线10.传输线10包括形成在基板11上的电介质膜13和形成在电介质膜13上的信号线。电介质膜13包括纳米复合膜其中第一材料的颗粒分散在第二材料中。

3. 发明授权

US07656010B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07656010B2
公开(公告)日：2010-02-02
申请号：US11898958
申请日：2007-09-18
申请人： Tomohiro Murata , Hiroaki Ueno , Hidetoshi Ishida , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Tomohiro Murata , Hiroaki Ueno , Hidetoshi Ishida , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L23/58
CPC分类号： H01L29/7787 , H01L23/367 , H01L23/3677 , H01L29/2003 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.
摘要翻译：半导体器件包括：半导体层; 形成在与半导体层接触的半导体层上的至少一个电极; 以及覆盖半导体层和电极的顶表面的至少一部分的钝化膜，以保护半导体层并由多个子膜形成。钝化膜包括由氮化铝制成的第一子膜。

4. 发明申请

US20070170463A1 Nitride semiconductor device 有权
标题翻译：氮化物半导体器件
公开(公告)号：US20070170463A1
公开(公告)日：2007-07-26
申请号：US11647218
申请日：2006-12-29
申请人： Hiroaki Ueno , Manabu Yanagihara , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Hiroaki Ueno , Manabu Yanagihara , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L31/00
CPC分类号： H01L29/7783 , H01L21/02381 , H01L21/0242 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/452 , H01L29/7787
摘要： A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.
摘要翻译：氮化物半导体器件包括：由第一氮化物半导体制成的第一半导体层; 第二半导体层，其形成在第一半导体层的主表面上并且由具有比第一氮化物半导体的带隙宽的第二氮化物半导体构成; 选择性地形成在所述第二半导体层的上部并且由上述第二半导体层的上部制成的具有p型导电性的第三氮化物半导体的控制层; 源极和漏极，形成在控制层的相应侧上的第二半导体层上; 形成在所述控制层上的栅电极; 以及形成在与所述主表面相对的所述第一半导体层的表面上的第四半导体层，所述第四半导体层相对于所述第一氮化物半导体具有价带中的势垒，并且由包含铝的第四氮化物半导体制成。

5. 发明授权

US07528423B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07528423B2
公开(公告)日：2009-05-05
申请号：US11681408
申请日：2007-03-02
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L31/072 , H01L31/109
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种可以同时实现HFET的常闭模式和改进Imax的半导体器件，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄的阻挡层13，主要用于实现常关模式并且还实现了高的Imax，它被配置成使得厚度可以通过栅极和源极区域之间以及栅极和漏极区域之间的半导体层17来增加阻挡层13。因此，与设置阻挡层的厚度均匀的FET相比，可以实现常闭模式和Imax的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而可以实现gm的改善和栅极漏电流的减小。

6. 发明申请

US20060157729A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060157729A1
公开(公告)日：2006-07-20
申请号：US11325340
申请日：2006-01-05
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L33/00
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max，配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅泄漏电流的降低可以实现。

7. 发明授权

US08203376B2 Semiconductor device and method for driving the same 有权
标题翻译：半导体装置及其驱动方法
公开(公告)号：US08203376B2
公开(公告)日：2012-06-19
申请号：US12445390
申请日：2007-11-20
申请人： Tatsuo Morita , Manabu Yanagihara , Hidetoshi Ishida , Yasuhiro Uemoto , Hiroaki Ueno , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Tatsuo Morita , Manabu Yanagihara , Hidetoshi Ishida , Yasuhiro Uemoto , Hiroaki Ueno , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H03K17/687
CPC分类号： H01L29/7787 , H01L27/0605 , H01L29/0619 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/739 , H01L29/8124
摘要： A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.
摘要翻译：半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

8. 发明授权

US08076698B2 Transistor and method for operating the same 有权
标题翻译：晶体管及其操作方法
公开(公告)号：US08076698B2
公开(公告)日：2011-12-13
申请号：US11995040
申请日：2006-06-27
申请人： Daisuke Ueda , Tsuyoshi Tanaka , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Masahiro Hikita , Hiroaki Ueno
发明人： Daisuke Ueda , Tsuyoshi Tanaka , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Masahiro Hikita , Hiroaki Ueno
IPC分类号： H01L31/0328
CPC分类号： H01L29/739 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/7786
摘要： In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.
摘要翻译：在晶体管中，在蓝宝石衬底101上依次形成AlN缓冲层102，未掺杂的GaN层103，未掺杂的AlGaN层104，p型控制层105和p型接触层106。晶体管还包括与p型接触层106欧姆接触的栅电极110以及设置在未掺杂的AlGaN层104上的源电极108和漏极109.通过向p型控制层105施加正电压，孔被注入到通道中以增加在通道中流动的电流。

9. 发明授权

US07825434B2 Nitride semiconductor device 有权
标题翻译：氮化物半导体器件
公开(公告)号：US07825434B2
公开(公告)日：2010-11-02
申请号：US11647218
申请日：2006-12-29
申请人： Hiroaki Ueno , Manabu Yanagihara , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Hiroaki Ueno , Manabu Yanagihara , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L29/08
CPC分类号： H01L29/7783 , H01L21/02381 , H01L21/0242 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/452 , H01L29/7787
摘要： A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.
摘要翻译：氮化物半导体器件包括：由第一氮化物半导体制成的第一半导体层; 第二半导体层，其形成在第一半导体层的主表面上并且由具有比第一氮化物半导体的带隙宽的第二氮化物半导体构成; 选择性地形成在所述第二半导体层的上部并且由上述第二半导体层的上部制成的具有p型导电性的第三氮化物半导体的控制层; 源极和漏极，形成在控制层的相应侧上的第二半导体层上; 形成在所述控制层上的栅电极; 以及第四半导体层，形成在与所述主表面相对的所述第一半导体层的表面上，相对于所述第一氮化物半导体具有价带中的势垒，并且由包含铝的第四氮化物半导体构成。

10. 发明申请

US20100327320A1 NITRIDE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：氮化物半导体器件
公开(公告)号：US20100327320A1
公开(公告)日：2010-12-30
申请号：US12879565
申请日：2010-09-10
申请人： Hiroaki Ueno , Manabu Yanagihara , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Hiroaki Ueno , Manabu Yanagihara , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L29/80
CPC分类号： H01L29/7783 , H01L21/02381 , H01L21/0242 , H01L21/02458 , H01L21/02502 , H01L21/0254 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/452 , H01L29/7787
摘要： A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.
摘要翻译：氮化物半导体器件包括：由第一氮化物半导体制成的第一半导体层; 第二半导体层，其形成在第一半导体层的主表面上并且由具有比第一氮化物半导体的带隙宽的第二氮化物半导体构成; 选择性地形成在所述第二半导体层的上部并且由上述第二半导体层的上部制成的具有p型导电性的第三氮化物半导体的控制层; 源极和漏极，形成在控制层的相应侧上的第二半导体层上; 形成在所述控制层上的栅电极; 以及形成在与所述主表面相对的所述第一半导体层的表面上的第四半导体层，所述第四半导体层相对于所述第一氮化物半导体具有价带中的势垒，并且由包含铝的第四氮化物半导体制成。

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