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1. 发明申请

US20090134498A1 SEMICONDUCTOR APPARATUS 审中-公开
公开(公告)号：US20090134498A1
公开(公告)日：2009-05-28
申请号：US12273590
申请日：2008-11-19
申请人： Hiroaki IKEDA , Masakazu Ishino , Hideharu Miyake , Shiro Uchiyama , Yasuhiro Naka , Nae Hisano , Hisashi Tanie , Kunihiko Nishi , Hiroyuki Tenmei
发明人： Hiroaki IKEDA , Masakazu Ishino , Hideharu Miyake , Shiro Uchiyama , Yasuhiro Naka , Nae Hisano , Hisashi Tanie , Kunihiko Nishi , Hiroyuki Tenmei
IPC分类号： H01L23/538 , H01L23/52 , H01L23/58
CPC分类号： H01L23/3128 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/11 , H01L24/12 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/1308 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/16 , H01L2224/2518 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2924/351 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material.
摘要翻译：本发明包括具有通过正面和背面的电极的半导体元件。电极形成为包括中空部分的圆柱体，并且应力松弛材料设置在中空部分中，其用于减小在半导体元件和电极之间感应的应力。应力松弛材料是由树脂材料制成的弹性体。

2. 发明申请

US20090109641A1 Wafer of circuit board and joining structure of wafer or circuit board 有权
标题翻译：电路板晶圆和晶圆或电路板的接合结构
公开(公告)号：US20090109641A1
公开(公告)日：2009-04-30
申请号：US12285222
申请日：2008-09-30
申请人： Masakazu Ishino , Hiroaki Ikeda , Hideharu Miyake , Shiro Uchiyama , Hiroyuki Tenmei , Kunihiko Nishi , Yasuhiro Naka , Nae Hisano
发明人： Masakazu Ishino , Hiroaki Ikeda , Hideharu Miyake , Shiro Uchiyama , Hiroyuki Tenmei , Kunihiko Nishi , Yasuhiro Naka , Nae Hisano
IPC分类号： H05K7/00
CPC分类号： H05K1/0296 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L24/90 , H01L25/0657 , H01L2224/03912 , H01L2224/0401 , H01L2224/05599 , H01L2224/1147 , H01L2224/11901 , H01L2224/11902 , H01L2224/13099 , H01L2224/13111 , H01L2224/2518 , H01L2224/81193 , H01L2224/81801 , H01L2224/90 , H01L2225/06513 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H05K1/09 , H05K3/3436 , H05K2201/0367 , H05K2201/10674 , Y02P70/613
摘要： A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.
摘要翻译：用于进行三维安装的晶片（或电路板）具有突起20，该突起20设置在用于电连接相互接合的晶片61和62的低熔点金属15中，并且限定相互连接的晶片之间的间隔 61和62，在低熔点金属15熔化时不变形。通过使用晶片61和62中的至少一个具有突起20来制造晶片61和62的接合结构。在制造的晶片61和62的接合结构中，晶片61和62通过低熔点彼此电连接点金属15和在低熔点金属15熔化时不会变形的晶片61和62之间的间隔的突起20设置在低熔点金属15中。

3. 发明授权

US08334465B2 Wafer of circuit board and joining structure of wafer or circuit board 有权
标题翻译：电路板晶圆和晶圆或电路板的接合结构
公开(公告)号：US08334465B2
公开(公告)日：2012-12-18
申请号：US12285222
申请日：2008-09-30
申请人： Masakazu Ishino , Hiroaki Ikeda , Hideharu Miyake , Shiro Uchiyama , Hiroyuki Tenmei , Kunihiko Nishi , Yasuhiro Naka , Nae Hisano
发明人： Masakazu Ishino , Hiroaki Ikeda , Hideharu Miyake , Shiro Uchiyama , Hiroyuki Tenmei , Kunihiko Nishi , Yasuhiro Naka , Nae Hisano
IPC分类号： H05K1/16 , H05K1/00 , H05K1/03 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K1/0296 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L24/90 , H01L25/0657 , H01L2224/03912 , H01L2224/0401 , H01L2224/05599 , H01L2224/1147 , H01L2224/11901 , H01L2224/11902 , H01L2224/13099 , H01L2224/13111 , H01L2224/2518 , H01L2224/81193 , H01L2224/81801 , H01L2224/90 , H01L2225/06513 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H05K1/09 , H05K3/3436 , H05K2201/0367 , H05K2201/10674 , Y02P70/613
摘要： A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.
摘要翻译：用于进行三维安装的晶片（或电路板）具有突起20，该突起20设置在用于电连接相互接合的晶片61和62的低熔点金属15中，并且限定相互连接的晶片之间的间隔 61和62，在低熔点金属15熔化时不变形。通过使用晶片61和62中的至少一个具有突起20来制造晶片61和62的接合结构。在制造的晶片61和62的接合结构中，晶片61和62通过低熔点彼此电连接点金属15和在低熔点金属15熔化时不会变形的晶片61和62之间的间隔的突起20设置在低熔点金属15中。

4. 发明授权

US08937390B2 Semiconductor device having a liquid cooling module 有权
标题翻译：具有液体冷却模块的半导体装置
公开(公告)号：US08937390B2
公开(公告)日：2015-01-20
申请号：US14199078
申请日：2014-03-06
申请人： Nae Hisano , Shigeo Ohashi , Yasuo Osone , Yasuhiro Naka , Hiroyuki Tenmei , Kunihiko Nishi , Hiroaki Ikeda , Masakazu Ishino , Hideharu Miyake , Shiro Uchiyama
发明人： Nae Hisano , Shigeo Ohashi , Yasuo Osone , Yasuhiro Naka , Hiroyuki Tenmei , Kunihiko Nishi , Hiroaki Ikeda , Masakazu Ishino , Hideharu Miyake , Shiro Uchiyama
IPC分类号： H01L23/48 , H01L23/02 , H01L23/00 , H01L23/31 , H01L23/473 , H01L23/34
CPC分类号： H01L24/14 , H01L23/3128 , H01L23/34 , H01L23/473 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2225/06565 , H01L2924/1461 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/00
摘要： A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
摘要翻译：半导体器件包括安装基板，设置在所述安装基板上方的半导体元件，设置在所述安装基板上方的封装基板，其间具有所述半导体元件，并通过主连接凸块与所述半导体元件电连接;冷却所述半导体液体制冷剂的热接收部分设置在所述半导体元件和所述安装基板之间，以及设置在所述封装基板和所述安装基板之间的多个次级连接凸块。

5. 发明授权

US08704352B2 Semiconductor device having a liquid cooling module 有权
标题翻译：具有液体冷却模块的半导体装置
公开(公告)号：US08704352B2
公开(公告)日：2014-04-22
申请号：US12683085
申请日：2010-01-06
申请人： Nae Hisano , Shigeo Ohashi , Yasuo Osone , Yasuhiro Naka , Hiroyuki Tenmei , Kunihiko Nishi , Hiroaki Ikeda , Masakazu Ishino , Hideharu Miyake , Shiro Uchiyama
发明人： Nae Hisano , Shigeo Ohashi , Yasuo Osone , Yasuhiro Naka , Hiroyuki Tenmei , Kunihiko Nishi , Hiroaki Ikeda , Masakazu Ishino , Hideharu Miyake , Shiro Uchiyama
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L24/14 , H01L23/3128 , H01L23/34 , H01L23/473 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2225/06565 , H01L2924/1461 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/18161 , H01L2924/00
摘要： A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.
摘要翻译：半导体器件包括安装基板，设置在所述安装基板上方的半导体元件，设置在所述安装基板上方的封装基板，其间具有所述半导体元件，并通过主连接凸块与所述半导体元件电连接;冷却所述半导体液体制冷剂的热接收部分设置在所述半导体元件和所述安装基板之间，以及设置在所述封装基板和所述安装基板之间的多个次级连接凸块。

6. 发明授权

US08004090B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08004090B2
公开(公告)日：2011-08-23
申请号：US12258547
申请日：2008-10-27
申请人： Shiro Uchiyama
发明人： Shiro Uchiyama
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/481 , H01L24/12 , H01L2221/68372 , H01L2224/05001 , H01L2224/05009 , H01L2224/05085 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05184 , H01L2224/05568 , H01L2224/0557 , H01L2224/13025 , H01L2224/13099 , H01L2224/13111 , H01L2224/2518 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/00014 , H01L2924/01028 , H01L2924/00
摘要： A first insulating layer including a first contact pad made of conductive polysilicon and a second insulating layer including a second contact pad are formed over a semiconductor silicon layer. After this, a via hole for a through-hole electrode is formed until the via hole penetrates through at least the semiconductor silicon layer and the first contact pad and reaches to the second contact pad.
摘要翻译：在半导体硅层上形成包括由导电多晶硅构成的第一接触焊盘和包括第二接触焊盘的第二绝缘层的第一绝缘层。此后，形成用于通孔电极的通孔，直到通孔至少穿过半导体硅层和第一接触焊盘并到达第二接触焊盘。

7. 发明授权

US07842610B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07842610B2
公开(公告)日：2010-11-30
申请号：US12000714
申请日：2007-12-17
申请人： Shiro Uchiyama
发明人： Shiro Uchiyama
IPC分类号： H01L21/44
CPC分类号： H01L25/0657 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05567 , H01L2224/0557 , H01L2224/16 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/3011 , H01L2224/05599 , H01L2224/05099
摘要： A through-electrode that penetrates a semiconductor substrate and that is insulatively separated from the semiconductor substrate includes an inner through-electrode, a quadrangular ring-shaped semiconductor, and an outer peripheral through-electrode. The quadrangular ring-shaped semiconductor is formed around the inner through-electrode, and the outer peripheral through-electrode is formed around the quadrangular ring-shaped semiconductor.
摘要翻译：穿透半导体衬底并且与半导体衬底绝缘分离的贯通电极包括内通孔，四边形环形半导体和外周通电极。四边形环状半导体形成在内部贯通电极的周围，外周贯通电极围绕四边形环状半导体形成。

8. 发明授权

US08722502B2 Chip-stacked semiconductor device and manufacturing method thereof 有权
标题翻译：芯片堆叠半导体器件及其制造方法
公开(公告)号：US08722502B2
公开(公告)日：2014-05-13
申请号：US13064757
申请日：2011-04-13
申请人： Shiro Uchiyama
发明人： Shiro Uchiyama
IPC分类号： H01L21/331
CPC分类号： H01L21/76264 , H01L21/76898 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： A method of manufacturing a semiconductor device, includes forming a trench surrounding a first area of a semiconductor substrate, the trench having a bottom surface and two side surfaces being opposite to each other, forming a silicon film on the bottom surface and side surfaces of the trench, forming an insulation film on the silicon film in the trench, grinding a bottom surface of the semiconductor substrate to expose the insulation film formed over the bottom surface of the trench, and forming a through electrode in the first area after grinding the bottom surface of the semiconductor substrate, the through electrode penetrating the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，包括形成围绕半导体衬底的第一区域的沟槽，所述沟槽具有底表面和两个彼此相对的侧表面，在所述沟槽的底表面和所述半导体衬底的侧表面上形成硅膜沟槽，在沟槽中的硅膜上形成绝缘膜，研磨半导体衬底的底表面以暴露形成在沟槽底表面上的绝缘膜，并且在研磨底表面之后在第一区域形成通孔所述贯通电极穿过所述半导体衬底。

9. 发明授权

US07943470B2 Chip-stacked semiconductor device and manufacturing method thereof 有权
标题翻译：芯片堆叠半导体器件及其制造方法
公开(公告)号：US07943470B2
公开(公告)日：2011-05-17
申请号：US12078295
申请日：2008-03-28
申请人： Shiro Uchiyama
发明人： Shiro Uchiyama
IPC分类号： H01L21/331 , H01L21/30
CPC分类号： H01L21/76264 , H01L21/76898 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： The semiconductor device according to the present invention includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a silicon film in contact with an inner surface of the isolation trench, a silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the silicon films. According to the present invention, the silicon film within the isolation trench can be substantially regarded as a part of the silicon substrate. Therefore, even when the width of the isolation trench is increased to increase the etching rate, the width of the insulation film becoming a dead space can be made sufficiently small. Consequently, the chip area can be decreased.
摘要翻译：根据本发明的半导体器件包括穿透硅衬底的穿透电极，设置成穿过硅衬底以包围通孔的隔离沟槽，与隔离沟槽的内表面接触的硅膜，与隔离沟槽的外表面接触的硅膜，以及设置在硅膜之间的绝缘膜。根据本发明，隔离沟槽内的硅膜可以基本上被认为是硅衬底的一部分。因此，即使增加隔离沟槽的宽度以增加蚀刻速率，也可以使成为死区的绝缘膜的宽度足够小。因此，可以减小芯片面积。

10. 发明授权

US07897459B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07897459B2
公开(公告)日：2011-03-01
申请号：US11857286
申请日：2007-09-18
申请人： Shiro Uchiyama
发明人： Shiro Uchiyama
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/76898
摘要： A through electrode is formed prior to fabricating a semiconductor device by using a standard manufacturing method. Aside face of the through electrode is insulated from a semiconductor substrate by an insulating film, while the top face thereof is covered with a protective insulating film. These insulating films covering the through electrode protect a conductor of the through electrode and prevent emission of a contaminant from the conductor. Standard manufacturing conditions can be applied without change.
摘要翻译：在通过使用标准制造方法制造半导体器件之前形成通孔电极。通过绝缘膜将通孔电极的侧面与半导体基板绝缘，同时其顶面被保护绝缘膜覆盖。覆盖通孔的这些绝缘膜保护通孔的导体，并防止污染物从导体发射。标准制造条件可以无变化地应用。

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